From: Huang Tao <eric.huang@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com,
dbarboza@ventanamicro.com, liwei1518@gmail.com,
bin.meng@windriver.com, alistair.francis@wdc.com,
palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com>
Subject: [PATCH 36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector
Date: Fri, 12 Apr 2024 15:37:06 +0800 [thread overview]
Message-ID: <20240412073735.76413-37-eric.huang@linux.alibaba.com> (raw)
In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com>
In this patch, we add single-width floating-point add/sub instructions
to show the way we implement XTheadVector floating-point arithmetic
instructions. XTheadVector diff from RVV1.0 in the following points:
1. Different mask reg layout.
2. Different tail/masked elements process policy.
3. Different check policy. XTheadVector does not have fractional lmul, so we can
use simpler check function.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 16 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 113 +++++++++++++++++-
target/riscv/vector_helper.c | 6 +-
target/riscv/vector_internals.h | 4 +
target/riscv/xtheadvector_helper.c | 106 ++++++++++++++++
5 files changed, 237 insertions(+), 8 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6254be771f..04bd363ac0 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1996,3 +1996,19 @@ DEF_HELPER_6(th_vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(th_vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 108f3249d0..a18c661f24 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -1746,17 +1746,120 @@ GEN_OPIVX_NARROW_TRANS_TH(th_vnclip_vx)
GEN_OPIVI_NARROW_TRANS_TH(th_vnclipu_vi, IMM_ZX, th_vnclipu_vx)
GEN_OPIVI_NARROW_TRANS_TH(th_vnclip_vi, IMM_ZX, th_vnclip_vx)
+/*
+ * Vector Float Point Arithmetic Instructions
+ */
+
+/* Vector Single-Width Floating-Point Add/Subtract Instructions */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised.
+ */
+static bool opfvv_check_th(DisasContext *s, arg_rmrr *a)
+{
+ return require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_overlap_mask(s, a->rd, a->vm, false) &&
+ th_check_reg(s, a->rd, false) &&
+ th_check_reg(s, a->rs2, false) &&
+ th_check_reg(s, a->rs1, false) &&
+ (s->sew != 0);
+}
+
+/*
+ * The macro below including GEN_OPFVV_TRANS_TH and GEN_OPFVF_TRANS_TH,
+ * are just changed the data encoding compared to RVV1.0.
+ */
+
+/* OPFVV without GVEC IR */
+#define GEN_OPFVV_TRANS_TH(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_4_ptr * const fns[3] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ gen_helper_##NAME##_d, \
+ }; \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ \
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), tcg_env, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
+ fns[s->sew - 1]); \
+ finalize_rvv_inst(s); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFVV_TRANS_TH(th_vfadd_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfsub_vv, opfvv_check_th)
+
+#define gen_helper_opfvf_th gen_helper_opfvf
+
+static bool opfvf_check_th(DisasContext *s, arg_rmrr *a)
+{
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+ return require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_overlap_mask(s, a->rd, a->vm, false) &&
+ th_check_reg(s, a->rd, false) &&
+ th_check_reg(s, a->rs2, false) &&
+ (s->sew != 0);
+}
+
+/*
+ * OPFVF without GVEC IR
+ *
+ * XTheadVector has different process policy when FLEN < SEW from
+ * RVV1.0. In XTheadVector, when FLEN < SEW, the value in freg should
+ * be nanboxed, while in RVV1.0, this situation is reserved.
+ * However, RVF-only cpus always have values NaN-boxed to 64-bits, so
+ * we do not have to deal with this situation differently. We can just
+ * use the RVV function opfvf_trans
+ */
+#define GEN_OPFVF_TRANS_TH(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_opfvf_th *const fns[3] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ gen_helper_##NAME##_d, \
+ }; \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); \
+ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
+ fns[s->sew - 1], s); \
+ } \
+ return false; \
+}
+
+GEN_OPFVF_TRANS_TH(th_vfadd_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfsub_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfrsub_vf, opfvf_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vfadd_vv)
-TH_TRANS_STUB(th_vfadd_vf)
-TH_TRANS_STUB(th_vfsub_vv)
-TH_TRANS_STUB(th_vfsub_vf)
-TH_TRANS_STUB(th_vfrsub_vf)
TH_TRANS_STUB(th_vfwadd_vv)
TH_TRANS_STUB(th_vfwadd_vf)
TH_TRANS_STUB(th_vfwadd_wv)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 262cb28824..3784096da2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2904,17 +2904,17 @@ GEN_VEXT_VF(vfsub_vf_h, 2)
GEN_VEXT_VF(vfsub_vf_w, 4)
GEN_VEXT_VF(vfsub_vf_d, 8)
-static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
+uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
{
return float16_sub(b, a, s);
}
-static uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s)
+uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s)
{
return float32_sub(b, a, s);
}
-static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
+uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
{
return float64_sub(b, a, s);
}
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index a42dc080ec..5f250ab7ba 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -340,4 +340,8 @@ uint8_t vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b);
uint16_t vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, uint16_t b);
uint32_t vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b);
+uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s);
+uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s);
+uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s);
+
#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index 2e97a95392..60811ca813 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -2590,3 +2590,109 @@ THCALL(TH_OPIVX2_RM, th_vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
GEN_TH_VX_RM(th_vnclipu_vx_b, 1, 1, clearb_th)
GEN_TH_VX_RM(th_vnclipu_vx_h, 2, 2, clearh_th)
GEN_TH_VX_RM(th_vnclipu_vx_w, 4, 4, clearl_th)
+
+/*
+ * Vector Float Point Arithmetic Instructions
+ */
+
+/* Vector Single-Width Floating-Point Add/Subtract Instructions */
+
+/*
+ * Some functions or macros are just the same as RVV1.0.
+ * But it is not worthy to extract them from RVV1.0, so we just copy
+ * them.
+ */
+#define TH_OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)\
+static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
+ CPURISCVState *env) \
+{ \
+ TX1 s1 = *((T1 *)vs1 + HS1(i)); \
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
+ *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status); \
+}
+
+#define GEN_TH_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+ uint32_t vlmax = th_maxsz(desc) / ESZ; \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ for (i = env->vstart; i < vl; i++) { \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ do_##NAME(vd, vs1, vs2, i, env); \
+ } \
+ env->vstart = 0; \
+ CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+}
+
+THCALL(TH_OPFVV2, th_vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
+THCALL(TH_OPFVV2, th_vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
+THCALL(TH_OPFVV2, th_vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
+GEN_TH_VV_ENV(th_vfadd_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfadd_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfadd_vv_d, 8, 8, clearq_th)
+
+#define TH_OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
+static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
+ CPURISCVState *env) \
+{ \
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
+ *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
+}
+
+#define GEN_TH_VF(NAME, ESZ, DSZ, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+ uint32_t vlmax = th_maxsz(desc) / ESZ; \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ for (i = env->vstart; i < vl; i++) { \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ do_##NAME(vd, s1, vs2, i, env); \
+ } \
+ env->vstart = 0; \
+ CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+}
+
+THCALL(TH_OPFVF2, th_vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
+THCALL(TH_OPFVF2, th_vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
+THCALL(TH_OPFVF2, th_vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
+GEN_TH_VF(th_vfadd_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfadd_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfadd_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV2, th_vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
+THCALL(TH_OPFVV2, th_vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
+THCALL(TH_OPFVV2, th_vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
+GEN_TH_VV_ENV(th_vfsub_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfsub_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfsub_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF2, th_vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
+THCALL(TH_OPFVF2, th_vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
+THCALL(TH_OPFVF2, th_vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
+GEN_TH_VF(th_vfsub_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfsub_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfsub_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVF2, th_vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
+THCALL(TH_OPFVF2, th_vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
+THCALL(TH_OPFVF2, th_vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
+GEN_TH_VF(th_vfrsub_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfrsub_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfrsub_vf_d, 8, 8, clearq_th)
--
2.44.0
next prev parent reply other threads:[~2024-04-12 8:52 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 7:36 [PATCH 00/65]target/riscv: Support XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation Huang Tao
2024-04-12 7:36 ` [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs Huang Tao
2024-04-12 7:36 ` [PATCH 03/65] target/riscv: Add properties for XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 05/65] target/riscv: Add mlen in DisasContext Huang Tao
2024-04-12 7:36 ` [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 07/65] target/riscv: implement th.vsetvl{i} " Huang Tao
2024-04-12 7:36 ` [PATCH 08/65] target/riscv: Add strided load instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 09/65] target/riscv: Add strided store " Huang Tao
2024-04-12 7:36 ` [PATCH 10/65] target/riscv: Add unit-stride load " Huang Tao
2024-04-12 7:36 ` [PATCH 11/65] target/riscv: Add unit-stride store " Huang Tao
2024-04-12 7:36 ` [PATCH 12/65] target/riscv: Add indexed load " Huang Tao
2024-04-12 7:36 ` [PATCH 13/65] target/riscv: Add indexed store " Huang Tao
2024-04-12 7:36 ` [PATCH 14/65] target/riscv: Add unit-stride fault-only-first " Huang Tao
2024-04-12 7:36 ` [PATCH 15/65] target/riscv: Add vector amo operations " Huang Tao
2024-04-12 7:36 ` [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 17/65] target/riscv: Add widening integer add/subtract " Huang Tao
2024-04-12 7:36 ` [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow " Huang Tao
2024-04-12 7:36 ` [PATCH 19/65] target/riscv: Add bitwise logical " Huang Tao
2024-04-12 7:36 ` [PATCH 20/65] target/riscv: Add single-width bit shift " Huang Tao
2024-04-12 7:36 ` [PATCH 21/65] target/riscv: Add narrowing integer right " Huang Tao
2024-04-12 7:36 ` [PATCH 22/65] target/riscv: Add integer compare " Huang Tao
2024-04-12 7:36 ` [PATCH 23/65] target/riscv: Add integer min/max " Huang Tao
2024-04-12 7:36 ` [PATCH 24/65] target/riscv: Add single-width integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 25/65] target/riscv: Add integer divide " Huang Tao
2024-04-12 7:36 ` [PATCH 26/65] target/riscv: Add widening integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 27/65] target/riscv: Add single-width integer multiply-add " Huang Tao
2024-04-12 7:36 ` [PATCH 28/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:36 ` [PATCH 29/65] target/riscv: Add integer merge and move " Huang Tao
2024-04-12 7:37 ` [PATCH 30/65] target/riscv: Add single-width saturating add and sub " Huang Tao
2024-04-12 7:37 ` [PATCH 31/65] target/riscv: Add single-width average " Huang Tao
2024-04-12 7:37 ` [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation " Huang Tao
2024-04-12 7:37 ` [PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 34/65] target/riscv: Add single-width scaling shift " Huang Tao
2024-04-12 7:37 ` [PATCH 35/65] target/riscv: Add narrowing fixed-point clip " Huang Tao
2024-04-12 7:37 ` Huang Tao [this message]
2024-04-12 7:37 ` [PATCH 37/65] target/riscv: Add widening floating-point add/sub " Huang Tao
2024-04-12 7:37 ` [PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide " Huang Tao
2024-04-12 7:37 ` [PATCH 39/65] target/riscv: Add widening floating-point multiply " Huang Tao
2024-04-12 7:37 ` [PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add " Huang Tao
2024-04-12 7:37 ` [PATCH 41/65] target/riscv: Add widening floating-point fused mul-add " Huang Tao
2024-04-12 7:37 ` [PATCH 42/65] target/riscv: Add floating-pointing square-root " Huang Tao
2024-04-12 7:37 ` [PATCH 43/65] target/riscv: Add floating-point MIN/MAX " Huang Tao
2024-04-12 7:37 ` [PATCH 44/65] target/riscv: Add floating-point sign-injection " Huang Tao
2024-04-12 7:37 ` [PATCH 45/65] target/riscv: Add floating-point compare " Huang Tao
2024-04-12 7:37 ` [PATCH 46/65] target/riscv: Add floating-point classify and merge " Huang Tao
2024-04-12 7:37 ` [PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert " Huang Tao
2024-04-12 7:37 ` [PATCH 48/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 49/65] target/riscv: Add narrowing " Huang Tao
2024-04-12 7:37 ` [PATCH 50/65] target/riscv: Add single-width integer reduction " Huang Tao
2024-04-12 7:37 ` [PATCH 51/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 52/65] target/riscv: Add single-width floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 53/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 54/65] target/riscv: Add mask-register logical " Huang Tao
2024-04-12 7:37 ` [PATCH 55/65] target/riscv: Add vector mask population count vmpopc " Huang Tao
2024-04-12 7:37 ` [PATCH 56/65] target/riscv: Add th.vmfirst.m " Huang Tao
2024-04-12 7:37 ` [PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions " Huang Tao
2024-04-12 7:37 ` [PATCH 58/65] target/riscv: Add vector iota instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 59/65] target/riscv: Add vector element index " Huang Tao
2024-04-12 7:37 ` [PATCH 60/65] target/riscv: Add integer extract and scalar move instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 61/65] target/riscv: Add floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 62/65] target/riscv: Add vector slide " Huang Tao
2024-04-12 7:37 ` [PATCH 63/65] target/riscv: Add vector register gather " Huang Tao
2024-04-12 7:37 ` [PATCH 64/65] target/riscv: Add vector compress instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 65/65] target/riscv: Enable XTheadVector extension for c906 Huang Tao
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