From: Huang Tao <eric.huang@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com,
dbarboza@ventanamicro.com, liwei1518@gmail.com,
bin.meng@windriver.com, alistair.francis@wdc.com,
palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com>
Subject: [PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add instructions for XTheadVector
Date: Fri, 12 Apr 2024 15:37:10 +0800 [thread overview]
Message-ID: <20240412073735.76413-41-eric.huang@linux.alibaba.com> (raw)
In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com>
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 49 +++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 34 ++---
target/riscv/vector_helper.c | 48 +++----
target/riscv/vector_internals.h | 25 ++++
target/riscv/xtheadvector_helper.c | 125 ++++++++++++++++++
5 files changed, 241 insertions(+), 40 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 3102b078e4..88e3a18e17 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2050,3 +2050,52 @@ DEF_HELPER_6(th_vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(th_vfmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfnmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 3d0370f220..af512c489b 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2019,28 +2019,30 @@ GEN_OPFVF_TRANS_TH(th_vfrdiv_vf, opfvf_check_th)
GEN_OPFVV_WIDEN_TRANS_TH(th_vfwmul_vv, opfvv_widen_check_th)
GEN_OPFVF_WIDEN_TRANS_TH(th_vfwmul_vf)
+/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
+GEN_OPFVV_TRANS_TH(th_vfmacc_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfnmacc_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfmsac_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfnmsac_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfmadd_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfnmadd_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfmsub_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfnmsub_vv, opfvv_check_th)
+GEN_OPFVF_TRANS_TH(th_vfmacc_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfnmacc_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfmsac_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfnmsac_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfmadd_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfnmadd_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfmsub_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfnmsub_vf, opfvf_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vfmacc_vv)
-TH_TRANS_STUB(th_vfnmacc_vv)
-TH_TRANS_STUB(th_vfnmacc_vf)
-TH_TRANS_STUB(th_vfmacc_vf)
-TH_TRANS_STUB(th_vfmsac_vv)
-TH_TRANS_STUB(th_vfmsac_vf)
-TH_TRANS_STUB(th_vfnmsac_vv)
-TH_TRANS_STUB(th_vfnmsac_vf)
-TH_TRANS_STUB(th_vfmadd_vv)
-TH_TRANS_STUB(th_vfmadd_vf)
-TH_TRANS_STUB(th_vfnmadd_vv)
-TH_TRANS_STUB(th_vfnmadd_vf)
-TH_TRANS_STUB(th_vfmsub_vv)
-TH_TRANS_STUB(th_vfmsub_vf)
-TH_TRANS_STUB(th_vfnmsub_vv)
-TH_TRANS_STUB(th_vfnmsub_vf)
TH_TRANS_STUB(th_vfwmacc_vv)
TH_TRANS_STUB(th_vfwmacc_vf)
TH_TRANS_STUB(th_vfwnmacc_vv)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aa7714d651..165221e08b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3091,17 +3091,17 @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
*((TD *)vd + HD(i)) = OP(s2, s1, d, &env->fp_status); \
}
-static uint16_t fmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+uint16_t fmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
return float16_muladd(a, b, d, 0, s);
}
-static uint32_t fmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
+uint32_t fmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
return float32_muladd(a, b, d, 0, s);
}
-static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
return float64_muladd(a, b, d, 0, s);
}
@@ -3129,19 +3129,19 @@ GEN_VEXT_VF(vfmacc_vf_h, 2)
GEN_VEXT_VF(vfmacc_vf_w, 4)
GEN_VEXT_VF(vfmacc_vf_d, 8)
-static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
return float16_muladd(a, b, d, float_muladd_negate_c |
float_muladd_negate_product, s);
}
-static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
+uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
return float32_muladd(a, b, d, float_muladd_negate_c |
float_muladd_negate_product, s);
}
-static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
return float64_muladd(a, b, d, float_muladd_negate_c |
float_muladd_negate_product, s);
@@ -3160,17 +3160,17 @@ GEN_VEXT_VF(vfnmacc_vf_h, 2)
GEN_VEXT_VF(vfnmacc_vf_w, 4)
GEN_VEXT_VF(vfnmacc_vf_d, 8)
-static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
return float16_muladd(a, b, d, float_muladd_negate_c, s);
}
-static uint32_t fmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
+uint32_t fmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
return float32_muladd(a, b, d, float_muladd_negate_c, s);
}
-static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
return float64_muladd(a, b, d, float_muladd_negate_c, s);
}
@@ -3188,17 +3188,17 @@ GEN_VEXT_VF(vfmsac_vf_h, 2)
GEN_VEXT_VF(vfmsac_vf_w, 4)
GEN_VEXT_VF(vfmsac_vf_d, 8)
-static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
return float16_muladd(a, b, d, float_muladd_negate_product, s);
}
-static uint32_t fnmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
+uint32_t fnmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
return float32_muladd(a, b, d, float_muladd_negate_product, s);
}
-static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
return float64_muladd(a, b, d, float_muladd_negate_product, s);
}
@@ -3216,17 +3216,17 @@ GEN_VEXT_VF(vfnmsac_vf_h, 2)
GEN_VEXT_VF(vfnmsac_vf_w, 4)
GEN_VEXT_VF(vfnmsac_vf_d, 8)
-static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
return float16_muladd(d, b, a, 0, s);
}
-static uint32_t fmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
+uint32_t fmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
return float32_muladd(d, b, a, 0, s);
}
-static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
return float64_muladd(d, b, a, 0, s);
}
@@ -3244,19 +3244,19 @@ GEN_VEXT_VF(vfmadd_vf_h, 2)
GEN_VEXT_VF(vfmadd_vf_w, 4)
GEN_VEXT_VF(vfmadd_vf_d, 8)
-static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
return float16_muladd(d, b, a, float_muladd_negate_c |
float_muladd_negate_product, s);
}
-static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
+uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
return float32_muladd(d, b, a, float_muladd_negate_c |
float_muladd_negate_product, s);
}
-static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
return float64_muladd(d, b, a, float_muladd_negate_c |
float_muladd_negate_product, s);
@@ -3275,17 +3275,17 @@ GEN_VEXT_VF(vfnmadd_vf_h, 2)
GEN_VEXT_VF(vfnmadd_vf_w, 4)
GEN_VEXT_VF(vfnmadd_vf_d, 8)
-static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
return float16_muladd(d, b, a, float_muladd_negate_c, s);
}
-static uint32_t fmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
+uint32_t fmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
return float32_muladd(d, b, a, float_muladd_negate_c, s);
}
-static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
return float64_muladd(d, b, a, float_muladd_negate_c, s);
}
@@ -3303,17 +3303,17 @@ GEN_VEXT_VF(vfmsub_vf_h, 2)
GEN_VEXT_VF(vfmsub_vf_w, 4)
GEN_VEXT_VF(vfmsub_vf_d, 8)
-static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
+uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
return float16_muladd(d, b, a, float_muladd_negate_product, s);
}
-static uint32_t fnmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
+uint32_t fnmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
return float32_muladd(d, b, a, float_muladd_negate_product, s);
}
-static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
+uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
return float64_muladd(d, b, a, float_muladd_negate_product, s);
}
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index 8903a894d7..5733640e0d 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -360,4 +360,29 @@ uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s);
uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s);
uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s);
+uint16_t fmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s);
+uint32_t fmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s);
+uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s);
+uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s);
+uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s);
+uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s);
+uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s);
+uint32_t fmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s);
+uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s);
+uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s);
+uint32_t fnmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s);
+uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s);
+uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s);
+uint32_t fmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s);
+uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s);
+uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s);
+uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s);
+uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s);
+uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s);
+uint32_t fmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s);
+uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s);
+uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s);
+uint32_t fnmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s);
+uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s);
+
#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index dd01d66933..1d2da6ffb7 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -2779,3 +2779,128 @@ THCALL(TH_OPFVF2, th_vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
THCALL(TH_OPFVF2, th_vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
GEN_TH_VF(th_vfwmul_vf_h, 2, 4, clearl_th)
GEN_TH_VF(th_vfwmul_vf_w, 4, 8, clearq_th)
+
+/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
+#define TH_OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
+static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
+ CPURISCVState *env) \
+{ \
+ TX1 s1 = *((T1 *)vs1 + HS1(i)); \
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
+ TD d = *((TD *)vd + HD(i)); \
+ *((TD *)vd + HD(i)) = OP(s2, s1, d, &env->fp_status); \
+}
+
+THCALL(TH_OPFVV3, th_vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
+THCALL(TH_OPFVV3, th_vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
+THCALL(TH_OPFVV3, th_vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
+GEN_TH_VV_ENV(th_vfmacc_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfmacc_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfmacc_vv_d, 8, 8, clearq_th)
+
+#define TH_OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
+static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
+ CPURISCVState *env) \
+{ \
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
+ TD d = *((TD *)vd + HD(i)); \
+ *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d, &env->fp_status);\
+}
+
+THCALL(TH_OPFVF3, th_vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16)
+THCALL(TH_OPFVF3, th_vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32)
+THCALL(TH_OPFVF3, th_vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64)
+GEN_TH_VF(th_vfmacc_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfmacc_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfmacc_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV3, th_vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
+THCALL(TH_OPFVV3, th_vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32)
+THCALL(TH_OPFVV3, th_vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64)
+GEN_TH_VV_ENV(th_vfnmacc_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfnmacc_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfnmacc_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF3, th_vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16)
+THCALL(TH_OPFVF3, th_vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32)
+THCALL(TH_OPFVF3, th_vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64)
+GEN_TH_VF(th_vfnmacc_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfnmacc_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfnmacc_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV3, th_vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16)
+THCALL(TH_OPFVV3, th_vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32)
+THCALL(TH_OPFVV3, th_vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64)
+GEN_TH_VV_ENV(th_vfmsac_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfmsac_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfmsac_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF3, th_vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16)
+THCALL(TH_OPFVF3, th_vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32)
+THCALL(TH_OPFVF3, th_vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64)
+GEN_TH_VF(th_vfmsac_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfmsac_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfmsac_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV3, th_vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16)
+THCALL(TH_OPFVV3, th_vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32)
+THCALL(TH_OPFVV3, th_vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64)
+GEN_TH_VV_ENV(th_vfnmsac_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfnmsac_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfnmsac_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF3, th_vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16)
+THCALL(TH_OPFVF3, th_vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32)
+THCALL(TH_OPFVF3, th_vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64)
+GEN_TH_VF(th_vfnmsac_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfnmsac_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfnmsac_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV3, th_vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16)
+THCALL(TH_OPFVV3, th_vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32)
+THCALL(TH_OPFVV3, th_vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64)
+GEN_TH_VV_ENV(th_vfmadd_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfmadd_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfmadd_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF3, th_vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16)
+THCALL(TH_OPFVF3, th_vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32)
+THCALL(TH_OPFVF3, th_vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64)
+GEN_TH_VF(th_vfmadd_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfmadd_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfmadd_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV3, th_vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
+THCALL(TH_OPFVV3, th_vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32)
+THCALL(TH_OPFVV3, th_vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64)
+GEN_TH_VV_ENV(th_vfnmadd_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfnmadd_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfnmadd_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF3, th_vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16)
+THCALL(TH_OPFVF3, th_vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32)
+THCALL(TH_OPFVF3, th_vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64)
+GEN_TH_VF(th_vfnmadd_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfnmadd_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfnmadd_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV3, th_vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16)
+THCALL(TH_OPFVV3, th_vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32)
+THCALL(TH_OPFVV3, th_vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64)
+GEN_TH_VV_ENV(th_vfmsub_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfmsub_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfmsub_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF3, th_vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16)
+THCALL(TH_OPFVF3, th_vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32)
+THCALL(TH_OPFVF3, th_vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64)
+GEN_TH_VF(th_vfmsub_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfmsub_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfmsub_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV3, th_vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16)
+THCALL(TH_OPFVV3, th_vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32)
+THCALL(TH_OPFVV3, th_vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64)
+GEN_TH_VV_ENV(th_vfnmsub_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfnmsub_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfnmsub_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF3, th_vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16)
+THCALL(TH_OPFVF3, th_vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32)
+THCALL(TH_OPFVF3, th_vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
+GEN_TH_VF(th_vfnmsub_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfnmsub_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfnmsub_vf_d, 8, 8, clearq_th)
--
2.44.0
next prev parent reply other threads:[~2024-04-12 9:16 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 7:36 [PATCH 00/65]target/riscv: Support XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation Huang Tao
2024-04-12 7:36 ` [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs Huang Tao
2024-04-12 7:36 ` [PATCH 03/65] target/riscv: Add properties for XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 05/65] target/riscv: Add mlen in DisasContext Huang Tao
2024-04-12 7:36 ` [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 07/65] target/riscv: implement th.vsetvl{i} " Huang Tao
2024-04-12 7:36 ` [PATCH 08/65] target/riscv: Add strided load instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 09/65] target/riscv: Add strided store " Huang Tao
2024-04-12 7:36 ` [PATCH 10/65] target/riscv: Add unit-stride load " Huang Tao
2024-04-12 7:36 ` [PATCH 11/65] target/riscv: Add unit-stride store " Huang Tao
2024-04-12 7:36 ` [PATCH 12/65] target/riscv: Add indexed load " Huang Tao
2024-04-12 7:36 ` [PATCH 13/65] target/riscv: Add indexed store " Huang Tao
2024-04-12 7:36 ` [PATCH 14/65] target/riscv: Add unit-stride fault-only-first " Huang Tao
2024-04-12 7:36 ` [PATCH 15/65] target/riscv: Add vector amo operations " Huang Tao
2024-04-12 7:36 ` [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 17/65] target/riscv: Add widening integer add/subtract " Huang Tao
2024-04-12 7:36 ` [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow " Huang Tao
2024-04-12 7:36 ` [PATCH 19/65] target/riscv: Add bitwise logical " Huang Tao
2024-04-12 7:36 ` [PATCH 20/65] target/riscv: Add single-width bit shift " Huang Tao
2024-04-12 7:36 ` [PATCH 21/65] target/riscv: Add narrowing integer right " Huang Tao
2024-04-12 7:36 ` [PATCH 22/65] target/riscv: Add integer compare " Huang Tao
2024-04-12 7:36 ` [PATCH 23/65] target/riscv: Add integer min/max " Huang Tao
2024-04-12 7:36 ` [PATCH 24/65] target/riscv: Add single-width integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 25/65] target/riscv: Add integer divide " Huang Tao
2024-04-12 7:36 ` [PATCH 26/65] target/riscv: Add widening integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 27/65] target/riscv: Add single-width integer multiply-add " Huang Tao
2024-04-12 7:36 ` [PATCH 28/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:36 ` [PATCH 29/65] target/riscv: Add integer merge and move " Huang Tao
2024-04-12 7:37 ` [PATCH 30/65] target/riscv: Add single-width saturating add and sub " Huang Tao
2024-04-12 7:37 ` [PATCH 31/65] target/riscv: Add single-width average " Huang Tao
2024-04-12 7:37 ` [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation " Huang Tao
2024-04-12 7:37 ` [PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 34/65] target/riscv: Add single-width scaling shift " Huang Tao
2024-04-12 7:37 ` [PATCH 35/65] target/riscv: Add narrowing fixed-point clip " Huang Tao
2024-04-12 7:37 ` [PATCH 36/65] target/riscv: Add single-width floating-point add/sub " Huang Tao
2024-04-12 7:37 ` [PATCH 37/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide " Huang Tao
2024-04-12 7:37 ` [PATCH 39/65] target/riscv: Add widening floating-point multiply " Huang Tao
2024-04-12 7:37 ` Huang Tao [this message]
2024-04-12 7:37 ` [PATCH 41/65] target/riscv: Add widening floating-point fused mul-add " Huang Tao
2024-04-12 7:37 ` [PATCH 42/65] target/riscv: Add floating-pointing square-root " Huang Tao
2024-04-12 7:37 ` [PATCH 43/65] target/riscv: Add floating-point MIN/MAX " Huang Tao
2024-04-12 7:37 ` [PATCH 44/65] target/riscv: Add floating-point sign-injection " Huang Tao
2024-04-12 7:37 ` [PATCH 45/65] target/riscv: Add floating-point compare " Huang Tao
2024-04-12 7:37 ` [PATCH 46/65] target/riscv: Add floating-point classify and merge " Huang Tao
2024-04-12 7:37 ` [PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert " Huang Tao
2024-04-12 7:37 ` [PATCH 48/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 49/65] target/riscv: Add narrowing " Huang Tao
2024-04-12 7:37 ` [PATCH 50/65] target/riscv: Add single-width integer reduction " Huang Tao
2024-04-12 7:37 ` [PATCH 51/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 52/65] target/riscv: Add single-width floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 53/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 54/65] target/riscv: Add mask-register logical " Huang Tao
2024-04-12 7:37 ` [PATCH 55/65] target/riscv: Add vector mask population count vmpopc " Huang Tao
2024-04-12 7:37 ` [PATCH 56/65] target/riscv: Add th.vmfirst.m " Huang Tao
2024-04-12 7:37 ` [PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions " Huang Tao
2024-04-12 7:37 ` [PATCH 58/65] target/riscv: Add vector iota instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 59/65] target/riscv: Add vector element index " Huang Tao
2024-04-12 7:37 ` [PATCH 60/65] target/riscv: Add integer extract and scalar move instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 61/65] target/riscv: Add floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 62/65] target/riscv: Add vector slide " Huang Tao
2024-04-12 7:37 ` [PATCH 63/65] target/riscv: Add vector register gather " Huang Tao
2024-04-12 7:37 ` [PATCH 64/65] target/riscv: Add vector compress instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 65/65] target/riscv: Enable XTheadVector extension for c906 Huang Tao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240412073735.76413-41-eric.huang@linux.alibaba.com \
--to=eric.huang@linux.alibaba.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).