From: Huang Tao <eric.huang@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com,
dbarboza@ventanamicro.com, liwei1518@gmail.com,
bin.meng@windriver.com, alistair.francis@wdc.com,
palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com>
Subject: [PATCH 45/65] target/riscv: Add floating-point compare instructions for XTheadVector
Date: Fri, 12 Apr 2024 15:37:15 +0800 [thread overview]
Message-ID: <20240412073735.76413-46-eric.huang@linux.alibaba.com> (raw)
In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com>
There is no similar instruction in RVV1.0 as th.vmford in XTheadVector.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 37 +++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 49 +++++++---
target/riscv/vector_helper.c | 18 ++--
target/riscv/vector_internals.h | 10 ++
target/riscv/xtheadvector_helper.c | 96 +++++++++++++++++++
5 files changed, 189 insertions(+), 21 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2b9d7fa2b6..5771a4fa8a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2152,3 +2152,40 @@ DEF_HELPER_6(th_vfsgnjn_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(th_vmfeq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfeq_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfeq_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfne_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfne_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfne_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmflt_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmflt_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmflt_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfle_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfle_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfle_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmfeq_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfeq_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfeq_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfne_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfne_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfne_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmflt_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmflt_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmflt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfle_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfle_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfle_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfgt_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfgt_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 1374bad5b9..1e773c673e 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2106,24 +2106,49 @@ GEN_OPFVF_TRANS_TH(th_vfsgnj_vf, opfvf_check_th)
GEN_OPFVF_TRANS_TH(th_vfsgnjn_vf, opfvf_check_th)
GEN_OPFVF_TRANS_TH(th_vfsgnjx_vf, opfvf_check_th)
+/* Vector Floating-Point Compare Instructions */
+static bool opfvv_cmp_check_th(DisasContext *s, arg_rmrr *a)
+{
+ return (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_reg(s, a->rs2, false) &&
+ th_check_reg(s, a->rs1, false) &&
+ (s->sew != 0) &&
+ ((th_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
+ th_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
+ (s->lmul == 0)));
+}
+
+GEN_OPFVV_TRANS_TH(th_vmfeq_vv, opfvv_cmp_check_th)
+GEN_OPFVV_TRANS_TH(th_vmfne_vv, opfvv_cmp_check_th)
+GEN_OPFVV_TRANS_TH(th_vmflt_vv, opfvv_cmp_check_th)
+GEN_OPFVV_TRANS_TH(th_vmfle_vv, opfvv_cmp_check_th)
+GEN_OPFVV_TRANS_TH(th_vmford_vv, opfvv_cmp_check_th)
+
+static bool opfvf_cmp_check_th(DisasContext *s, arg_rmrr *a)
+{
+ return (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_reg(s, a->rs2, false) &&
+ (s->sew != 0) &&
+ (th_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
+ (s->lmul == 0)));
+}
+
+GEN_OPFVF_TRANS_TH(th_vmfeq_vf, opfvf_cmp_check_th)
+GEN_OPFVF_TRANS_TH(th_vmfne_vf, opfvf_cmp_check_th)
+GEN_OPFVF_TRANS_TH(th_vmflt_vf, opfvf_cmp_check_th)
+GEN_OPFVF_TRANS_TH(th_vmfle_vf, opfvf_cmp_check_th)
+GEN_OPFVF_TRANS_TH(th_vmfgt_vf, opfvf_cmp_check_th)
+GEN_OPFVF_TRANS_TH(th_vmfge_vf, opfvf_cmp_check_th)
+GEN_OPFVF_TRANS_TH(th_vmford_vf, opfvf_cmp_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vmfeq_vv)
-TH_TRANS_STUB(th_vmfeq_vf)
-TH_TRANS_STUB(th_vmfne_vv)
-TH_TRANS_STUB(th_vmfne_vf)
-TH_TRANS_STUB(th_vmflt_vv)
-TH_TRANS_STUB(th_vmflt_vf)
-TH_TRANS_STUB(th_vmfle_vv)
-TH_TRANS_STUB(th_vmfle_vf)
-TH_TRANS_STUB(th_vmfgt_vf)
-TH_TRANS_STUB(th_vmfge_vf)
-TH_TRANS_STUB(th_vmford_vv)
-TH_TRANS_STUB(th_vmford_vf)
TH_TRANS_STUB(th_vfclass_v)
TH_TRANS_STUB(th_vfmerge_vfm)
TH_TRANS_STUB(th_vfmv_v_f)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d0ebda5445..c966600d0c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4050,19 +4050,19 @@ GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet)
GEN_VEXT_CMP_VF(vmfeq_vf_w, uint32_t, H4, float32_eq_quiet)
GEN_VEXT_CMP_VF(vmfeq_vf_d, uint64_t, H8, float64_eq_quiet)
-static bool vmfne16(uint16_t a, uint16_t b, float_status *s)
+bool vmfne16(uint16_t a, uint16_t b, float_status *s)
{
FloatRelation compare = float16_compare_quiet(a, b, s);
return compare != float_relation_equal;
}
-static bool vmfne32(uint32_t a, uint32_t b, float_status *s)
+bool vmfne32(uint32_t a, uint32_t b, float_status *s)
{
FloatRelation compare = float32_compare_quiet(a, b, s);
return compare != float_relation_equal;
}
-static bool vmfne64(uint64_t a, uint64_t b, float_status *s)
+bool vmfne64(uint64_t a, uint64_t b, float_status *s)
{
FloatRelation compare = float64_compare_quiet(a, b, s);
return compare != float_relation_equal;
@@ -4089,19 +4089,19 @@ GEN_VEXT_CMP_VF(vmfle_vf_h, uint16_t, H2, float16_le)
GEN_VEXT_CMP_VF(vmfle_vf_w, uint32_t, H4, float32_le)
GEN_VEXT_CMP_VF(vmfle_vf_d, uint64_t, H8, float64_le)
-static bool vmfgt16(uint16_t a, uint16_t b, float_status *s)
+bool vmfgt16(uint16_t a, uint16_t b, float_status *s)
{
FloatRelation compare = float16_compare(a, b, s);
return compare == float_relation_greater;
}
-static bool vmfgt32(uint32_t a, uint32_t b, float_status *s)
+bool vmfgt32(uint32_t a, uint32_t b, float_status *s)
{
FloatRelation compare = float32_compare(a, b, s);
return compare == float_relation_greater;
}
-static bool vmfgt64(uint64_t a, uint64_t b, float_status *s)
+bool vmfgt64(uint64_t a, uint64_t b, float_status *s)
{
FloatRelation compare = float64_compare(a, b, s);
return compare == float_relation_greater;
@@ -4111,21 +4111,21 @@ GEN_VEXT_CMP_VF(vmfgt_vf_h, uint16_t, H2, vmfgt16)
GEN_VEXT_CMP_VF(vmfgt_vf_w, uint32_t, H4, vmfgt32)
GEN_VEXT_CMP_VF(vmfgt_vf_d, uint64_t, H8, vmfgt64)
-static bool vmfge16(uint16_t a, uint16_t b, float_status *s)
+bool vmfge16(uint16_t a, uint16_t b, float_status *s)
{
FloatRelation compare = float16_compare(a, b, s);
return compare == float_relation_greater ||
compare == float_relation_equal;
}
-static bool vmfge32(uint32_t a, uint32_t b, float_status *s)
+bool vmfge32(uint32_t a, uint32_t b, float_status *s)
{
FloatRelation compare = float32_compare(a, b, s);
return compare == float_relation_greater ||
compare == float_relation_equal;
}
-static bool vmfge64(uint64_t a, uint64_t b, float_status *s)
+bool vmfge64(uint64_t a, uint64_t b, float_status *s)
{
FloatRelation compare = float64_compare(a, b, s);
return compare == float_relation_greater ||
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index bcc7d0edd6..b870e15392 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -404,4 +404,14 @@ uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s);
uint32_t fsgnjx32(uint32_t a, uint32_t b, float_status *s);
uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s);
+bool vmfne16(uint16_t a, uint16_t b, float_status *s);
+bool vmfne32(uint32_t a, uint32_t b, float_status *s);
+bool vmfne64(uint64_t a, uint64_t b, float_status *s);
+bool vmfgt16(uint16_t a, uint16_t b, float_status *s);
+bool vmfgt32(uint32_t a, uint32_t b, float_status *s);
+bool vmfgt64(uint64_t a, uint64_t b, float_status *s);
+bool vmfge16(uint16_t a, uint16_t b, float_status *s);
+bool vmfge32(uint32_t a, uint32_t b, float_status *s);
+bool vmfge64(uint64_t a, uint64_t b, float_status *s);
+
#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index 38476900a6..603b34a094 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3051,3 +3051,99 @@ THCALL(TH_OPFVF2, th_vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
GEN_TH_VF(th_vfsgnjx_vf_h, 2, 2, clearh_th)
GEN_TH_VF(th_vfsgnjx_vf_w, 4, 4, clearl_th)
GEN_TH_VF(th_vfsgnjx_vf_d, 8, 8, clearq_th)
+
+/* Vector Floating-Point Compare Instructions */
+#define GEN_TH_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = th_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t i; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ for (i = env->vstart; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ th_set_elem_mask(vd, mlen, i, \
+ DO_OP(s2, s1, &env->fp_status)); \
+ } \
+ env->vstart = 0; \
+ for (; i < vlmax; i++) { \
+ th_set_elem_mask(vd, mlen, i, 0); \
+ } \
+}
+
+GEN_TH_CMP_VV_ENV(th_vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
+GEN_TH_CMP_VV_ENV(th_vmfeq_vv_w, uint32_t, H4, float32_eq_quiet)
+GEN_TH_CMP_VV_ENV(th_vmfeq_vv_d, uint64_t, H8, float64_eq_quiet)
+
+#define GEN_TH_CMP_VF(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = th_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t i; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ for (i = env->vstart; i < vl; i++) { \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ th_set_elem_mask(vd, mlen, i, \
+ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
+ } \
+ env->vstart = 0; \
+ for (; i < vlmax; i++) { \
+ th_set_elem_mask(vd, mlen, i, 0); \
+ } \
+}
+
+GEN_TH_CMP_VF(th_vmfeq_vf_h, uint16_t, H2, float16_eq_quiet)
+GEN_TH_CMP_VF(th_vmfeq_vf_w, uint32_t, H4, float32_eq_quiet)
+GEN_TH_CMP_VF(th_vmfeq_vf_d, uint64_t, H8, float64_eq_quiet)
+
+GEN_TH_CMP_VV_ENV(th_vmfne_vv_h, uint16_t, H2, vmfne16)
+GEN_TH_CMP_VV_ENV(th_vmfne_vv_w, uint32_t, H4, vmfne32)
+GEN_TH_CMP_VV_ENV(th_vmfne_vv_d, uint64_t, H8, vmfne64)
+GEN_TH_CMP_VF(th_vmfne_vf_h, uint16_t, H2, vmfne16)
+GEN_TH_CMP_VF(th_vmfne_vf_w, uint32_t, H4, vmfne32)
+GEN_TH_CMP_VF(th_vmfne_vf_d, uint64_t, H8, vmfne64)
+
+GEN_TH_CMP_VV_ENV(th_vmflt_vv_h, uint16_t, H2, float16_lt)
+GEN_TH_CMP_VV_ENV(th_vmflt_vv_w, uint32_t, H4, float32_lt)
+GEN_TH_CMP_VV_ENV(th_vmflt_vv_d, uint64_t, H8, float64_lt)
+GEN_TH_CMP_VF(th_vmflt_vf_h, uint16_t, H2, float16_lt)
+GEN_TH_CMP_VF(th_vmflt_vf_w, uint32_t, H4, float32_lt)
+GEN_TH_CMP_VF(th_vmflt_vf_d, uint64_t, H8, float64_lt)
+
+GEN_TH_CMP_VV_ENV(th_vmfle_vv_h, uint16_t, H2, float16_le)
+GEN_TH_CMP_VV_ENV(th_vmfle_vv_w, uint32_t, H4, float32_le)
+GEN_TH_CMP_VV_ENV(th_vmfle_vv_d, uint64_t, H8, float64_le)
+GEN_TH_CMP_VF(th_vmfle_vf_h, uint16_t, H2, float16_le)
+GEN_TH_CMP_VF(th_vmfle_vf_w, uint32_t, H4, float32_le)
+GEN_TH_CMP_VF(th_vmfle_vf_d, uint64_t, H8, float64_le)
+
+GEN_TH_CMP_VF(th_vmfgt_vf_h, uint16_t, H2, vmfgt16)
+GEN_TH_CMP_VF(th_vmfgt_vf_w, uint32_t, H4, vmfgt32)
+GEN_TH_CMP_VF(th_vmfgt_vf_d, uint64_t, H8, vmfgt64)
+
+GEN_TH_CMP_VF(th_vmfge_vf_h, uint16_t, H2, vmfge16)
+GEN_TH_CMP_VF(th_vmfge_vf_w, uint32_t, H4, vmfge32)
+GEN_TH_CMP_VF(th_vmfge_vf_d, uint64_t, H8, vmfge64)
+
+GEN_TH_CMP_VV_ENV(th_vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
+GEN_TH_CMP_VV_ENV(th_vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
+GEN_TH_CMP_VV_ENV(th_vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
+GEN_TH_CMP_VF(th_vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
+GEN_TH_CMP_VF(th_vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
+GEN_TH_CMP_VF(th_vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
--
2.44.0
next prev parent reply other threads:[~2024-04-12 9:26 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 7:36 [PATCH 00/65]target/riscv: Support XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation Huang Tao
2024-04-12 7:36 ` [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs Huang Tao
2024-04-12 7:36 ` [PATCH 03/65] target/riscv: Add properties for XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 05/65] target/riscv: Add mlen in DisasContext Huang Tao
2024-04-12 7:36 ` [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 07/65] target/riscv: implement th.vsetvl{i} " Huang Tao
2024-04-12 7:36 ` [PATCH 08/65] target/riscv: Add strided load instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 09/65] target/riscv: Add strided store " Huang Tao
2024-04-12 7:36 ` [PATCH 10/65] target/riscv: Add unit-stride load " Huang Tao
2024-04-12 7:36 ` [PATCH 11/65] target/riscv: Add unit-stride store " Huang Tao
2024-04-12 7:36 ` [PATCH 12/65] target/riscv: Add indexed load " Huang Tao
2024-04-12 7:36 ` [PATCH 13/65] target/riscv: Add indexed store " Huang Tao
2024-04-12 7:36 ` [PATCH 14/65] target/riscv: Add unit-stride fault-only-first " Huang Tao
2024-04-12 7:36 ` [PATCH 15/65] target/riscv: Add vector amo operations " Huang Tao
2024-04-12 7:36 ` [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 17/65] target/riscv: Add widening integer add/subtract " Huang Tao
2024-04-12 7:36 ` [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow " Huang Tao
2024-04-12 7:36 ` [PATCH 19/65] target/riscv: Add bitwise logical " Huang Tao
2024-04-12 7:36 ` [PATCH 20/65] target/riscv: Add single-width bit shift " Huang Tao
2024-04-12 7:36 ` [PATCH 21/65] target/riscv: Add narrowing integer right " Huang Tao
2024-04-12 7:36 ` [PATCH 22/65] target/riscv: Add integer compare " Huang Tao
2024-04-12 7:36 ` [PATCH 23/65] target/riscv: Add integer min/max " Huang Tao
2024-04-12 7:36 ` [PATCH 24/65] target/riscv: Add single-width integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 25/65] target/riscv: Add integer divide " Huang Tao
2024-04-12 7:36 ` [PATCH 26/65] target/riscv: Add widening integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 27/65] target/riscv: Add single-width integer multiply-add " Huang Tao
2024-04-12 7:36 ` [PATCH 28/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:36 ` [PATCH 29/65] target/riscv: Add integer merge and move " Huang Tao
2024-04-12 7:37 ` [PATCH 30/65] target/riscv: Add single-width saturating add and sub " Huang Tao
2024-04-12 7:37 ` [PATCH 31/65] target/riscv: Add single-width average " Huang Tao
2024-04-12 7:37 ` [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation " Huang Tao
2024-04-12 7:37 ` [PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 34/65] target/riscv: Add single-width scaling shift " Huang Tao
2024-04-12 7:37 ` [PATCH 35/65] target/riscv: Add narrowing fixed-point clip " Huang Tao
2024-04-12 7:37 ` [PATCH 36/65] target/riscv: Add single-width floating-point add/sub " Huang Tao
2024-04-12 7:37 ` [PATCH 37/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide " Huang Tao
2024-04-12 7:37 ` [PATCH 39/65] target/riscv: Add widening floating-point multiply " Huang Tao
2024-04-12 7:37 ` [PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add " Huang Tao
2024-04-12 7:37 ` [PATCH 41/65] target/riscv: Add widening floating-point fused mul-add " Huang Tao
2024-04-12 7:37 ` [PATCH 42/65] target/riscv: Add floating-pointing square-root " Huang Tao
2024-04-12 7:37 ` [PATCH 43/65] target/riscv: Add floating-point MIN/MAX " Huang Tao
2024-04-12 7:37 ` [PATCH 44/65] target/riscv: Add floating-point sign-injection " Huang Tao
2024-04-12 7:37 ` Huang Tao [this message]
2024-04-12 7:37 ` [PATCH 46/65] target/riscv: Add floating-point classify and merge " Huang Tao
2024-04-12 7:37 ` [PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert " Huang Tao
2024-04-12 7:37 ` [PATCH 48/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 49/65] target/riscv: Add narrowing " Huang Tao
2024-04-12 7:37 ` [PATCH 50/65] target/riscv: Add single-width integer reduction " Huang Tao
2024-04-12 7:37 ` [PATCH 51/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 52/65] target/riscv: Add single-width floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 53/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 54/65] target/riscv: Add mask-register logical " Huang Tao
2024-04-12 7:37 ` [PATCH 55/65] target/riscv: Add vector mask population count vmpopc " Huang Tao
2024-04-12 7:37 ` [PATCH 56/65] target/riscv: Add th.vmfirst.m " Huang Tao
2024-04-12 7:37 ` [PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions " Huang Tao
2024-04-12 7:37 ` [PATCH 58/65] target/riscv: Add vector iota instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 59/65] target/riscv: Add vector element index " Huang Tao
2024-04-12 7:37 ` [PATCH 60/65] target/riscv: Add integer extract and scalar move instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 61/65] target/riscv: Add floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 62/65] target/riscv: Add vector slide " Huang Tao
2024-04-12 7:37 ` [PATCH 63/65] target/riscv: Add vector register gather " Huang Tao
2024-04-12 7:37 ` [PATCH 64/65] target/riscv: Add vector compress instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 65/65] target/riscv: Enable XTheadVector extension for c906 Huang Tao
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