From: Huang Tao <eric.huang@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com,
dbarboza@ventanamicro.com, liwei1518@gmail.com,
bin.meng@windriver.com, alistair.francis@wdc.com,
palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com>
Subject: [PATCH 53/65] target/riscv: Add widening floating-point reduction instructions for XTheadVector
Date: Fri, 12 Apr 2024 15:37:23 +0800 [thread overview]
Message-ID: <20240412073735.76413-54-eric.huang@linux.alibaba.com> (raw)
In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com>
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 3 +++
target/riscv/insn_trans/trans_xtheadvector.c.inc | 4 +++-
target/riscv/xtheadvector_helper.c | 16 ++++++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 24bb8479a4..c39ee9a8e8 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2286,3 +2286,6 @@ DEF_HELPER_6(th_vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(th_vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index f77d76dc5e..b71875700b 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2402,13 +2402,15 @@ GEN_OPFVV_TRANS_TH(th_vfredsum_vs, reduction_check_th)
GEN_OPFVV_TRANS_TH(th_vfredmax_vs, reduction_check_th)
GEN_OPFVV_TRANS_TH(th_vfredmin_vs, reduction_check_th)
+/* Vector Widening Floating-Point Reduction Instructions */
+GEN_OPFVV_WIDEN_TRANS_TH(th_vfwredsum_vs, reduction_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vfwredsum_vs)
TH_TRANS_STUB(th_vmand_mm)
TH_TRANS_STUB(th_vmnand_mm)
TH_TRANS_STUB(th_vmandnot_mm)
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index 2a241aed65..8953207630 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3459,3 +3459,19 @@ GEN_TH_FRED(th_vfredmin_vs_w, uint32_t, uint32_t, H4, H4,
float32_minnum, clearl_th)
GEN_TH_FRED(th_vfredmin_vs_d, uint64_t, uint64_t, H8, H8,
float64_minnum, clearq_th)
+
+/* Vector Widening Floating-Point Add functions */
+static uint32_t fwadd16(uint32_t a, uint16_t b, float_status *s)
+{
+ return float32_add(a, float16_to_float32(b, true, s), s);
+}
+
+static uint64_t fwadd32(uint64_t a, uint32_t b, float_status *s)
+{
+ return float64_add(a, float32_to_float64(b, s), s);
+}
+
+/* Vector Widening Floating-Point Reduction Instructions */
+/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
+GEN_TH_FRED(th_vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16, clearl_th)
+GEN_TH_FRED(th_vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32, clearq_th)
--
2.44.0
next prev parent reply other threads:[~2024-04-12 9:42 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 7:36 [PATCH 00/65]target/riscv: Support XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation Huang Tao
2024-04-12 7:36 ` [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs Huang Tao
2024-04-12 7:36 ` [PATCH 03/65] target/riscv: Add properties for XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 05/65] target/riscv: Add mlen in DisasContext Huang Tao
2024-04-12 7:36 ` [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 07/65] target/riscv: implement th.vsetvl{i} " Huang Tao
2024-04-12 7:36 ` [PATCH 08/65] target/riscv: Add strided load instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 09/65] target/riscv: Add strided store " Huang Tao
2024-04-12 7:36 ` [PATCH 10/65] target/riscv: Add unit-stride load " Huang Tao
2024-04-12 7:36 ` [PATCH 11/65] target/riscv: Add unit-stride store " Huang Tao
2024-04-12 7:36 ` [PATCH 12/65] target/riscv: Add indexed load " Huang Tao
2024-04-12 7:36 ` [PATCH 13/65] target/riscv: Add indexed store " Huang Tao
2024-04-12 7:36 ` [PATCH 14/65] target/riscv: Add unit-stride fault-only-first " Huang Tao
2024-04-12 7:36 ` [PATCH 15/65] target/riscv: Add vector amo operations " Huang Tao
2024-04-12 7:36 ` [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 17/65] target/riscv: Add widening integer add/subtract " Huang Tao
2024-04-12 7:36 ` [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow " Huang Tao
2024-04-12 7:36 ` [PATCH 19/65] target/riscv: Add bitwise logical " Huang Tao
2024-04-12 7:36 ` [PATCH 20/65] target/riscv: Add single-width bit shift " Huang Tao
2024-04-12 7:36 ` [PATCH 21/65] target/riscv: Add narrowing integer right " Huang Tao
2024-04-12 7:36 ` [PATCH 22/65] target/riscv: Add integer compare " Huang Tao
2024-04-12 7:36 ` [PATCH 23/65] target/riscv: Add integer min/max " Huang Tao
2024-04-12 7:36 ` [PATCH 24/65] target/riscv: Add single-width integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 25/65] target/riscv: Add integer divide " Huang Tao
2024-04-12 7:36 ` [PATCH 26/65] target/riscv: Add widening integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 27/65] target/riscv: Add single-width integer multiply-add " Huang Tao
2024-04-12 7:36 ` [PATCH 28/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:36 ` [PATCH 29/65] target/riscv: Add integer merge and move " Huang Tao
2024-04-12 7:37 ` [PATCH 30/65] target/riscv: Add single-width saturating add and sub " Huang Tao
2024-04-12 7:37 ` [PATCH 31/65] target/riscv: Add single-width average " Huang Tao
2024-04-12 7:37 ` [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation " Huang Tao
2024-04-12 7:37 ` [PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 34/65] target/riscv: Add single-width scaling shift " Huang Tao
2024-04-12 7:37 ` [PATCH 35/65] target/riscv: Add narrowing fixed-point clip " Huang Tao
2024-04-12 7:37 ` [PATCH 36/65] target/riscv: Add single-width floating-point add/sub " Huang Tao
2024-04-12 7:37 ` [PATCH 37/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide " Huang Tao
2024-04-12 7:37 ` [PATCH 39/65] target/riscv: Add widening floating-point multiply " Huang Tao
2024-04-12 7:37 ` [PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add " Huang Tao
2024-04-12 7:37 ` [PATCH 41/65] target/riscv: Add widening floating-point fused mul-add " Huang Tao
2024-04-12 7:37 ` [PATCH 42/65] target/riscv: Add floating-pointing square-root " Huang Tao
2024-04-12 7:37 ` [PATCH 43/65] target/riscv: Add floating-point MIN/MAX " Huang Tao
2024-04-12 7:37 ` [PATCH 44/65] target/riscv: Add floating-point sign-injection " Huang Tao
2024-04-12 7:37 ` [PATCH 45/65] target/riscv: Add floating-point compare " Huang Tao
2024-04-12 7:37 ` [PATCH 46/65] target/riscv: Add floating-point classify and merge " Huang Tao
2024-04-12 7:37 ` [PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert " Huang Tao
2024-04-12 7:37 ` [PATCH 48/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 49/65] target/riscv: Add narrowing " Huang Tao
2024-04-12 7:37 ` [PATCH 50/65] target/riscv: Add single-width integer reduction " Huang Tao
2024-04-12 7:37 ` [PATCH 51/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 52/65] target/riscv: Add single-width floating-point " Huang Tao
2024-04-12 7:37 ` Huang Tao [this message]
2024-04-12 7:37 ` [PATCH 54/65] target/riscv: Add mask-register logical " Huang Tao
2024-04-12 7:37 ` [PATCH 55/65] target/riscv: Add vector mask population count vmpopc " Huang Tao
2024-04-12 7:37 ` [PATCH 56/65] target/riscv: Add th.vmfirst.m " Huang Tao
2024-04-12 7:37 ` [PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions " Huang Tao
2024-04-12 7:37 ` [PATCH 58/65] target/riscv: Add vector iota instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 59/65] target/riscv: Add vector element index " Huang Tao
2024-04-12 7:37 ` [PATCH 60/65] target/riscv: Add integer extract and scalar move instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 61/65] target/riscv: Add floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 62/65] target/riscv: Add vector slide " Huang Tao
2024-04-12 7:37 ` [PATCH 63/65] target/riscv: Add vector register gather " Huang Tao
2024-04-12 7:37 ` [PATCH 64/65] target/riscv: Add vector compress instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 65/65] target/riscv: Enable XTheadVector extension for c906 Huang Tao
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