From: Huang Tao <eric.huang@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com,
dbarboza@ventanamicro.com, liwei1518@gmail.com,
bin.meng@windriver.com, alistair.francis@wdc.com,
palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com>
Subject: [PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions for XTheadVector
Date: Fri, 12 Apr 2024 15:37:27 +0800 [thread overview]
Message-ID: <20240412073735.76413-58-eric.huang@linux.alibaba.com> (raw)
In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com>
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 4 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 36 ++++++++++-
target/riscv/xtheadvector_helper.c | 64 +++++++++++++++++++
3 files changed, 101 insertions(+), 3 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2379a3431d..90a1ff2601 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2302,3 +2302,7 @@ DEF_HELPER_6(th_vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(th_vmpopc_m, tl, ptr, ptr, env, i32)
DEF_HELPER_4(th_vmfirst_m, tl, ptr, ptr, env, i32)
+
+DEF_HELPER_5(th_vmsbf_m, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vmsif_m, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vmsof_m, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 45554c38fb..d41c691c31 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2500,6 +2500,39 @@ static bool trans_th_vmfirst_m(DisasContext *s, arg_rmr *a)
}
return false;
}
+/*
+ * th.vmsbf.m set-before-first mask bit
+ * th.vmsif.m set-including-first mask bit
+ * th.vmsof.m set-only-first mask bit
+ */
+#define GEN_M_TRANS_TH(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (require_xtheadvector(s) && \
+ vext_check_isa_ill(s) && \
+ (a->rd != a->rs2) && \
+ s->vstart_eq_zero) { \
+ uint32_t data = 0; \
+ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
+ \
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), \
+ tcg_env, s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, \
+ data, fn); \
+ finalize_rvv_inst(s); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_M_TRANS_TH(th_vmsbf_m)
+GEN_M_TRANS_TH(th_vmsif_m)
+GEN_M_TRANS_TH(th_vmsof_m)
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
@@ -2507,9 +2540,6 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vmsbf_m)
-TH_TRANS_STUB(th_vmsif_m)
-TH_TRANS_STUB(th_vmsof_m)
TH_TRANS_STUB(th_viota_m)
TH_TRANS_STUB(th_vid_v)
TH_TRANS_STUB(th_vext_x_v)
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index 1860e47f4f..d4f1665bf3 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3558,3 +3558,67 @@ target_ulong HELPER(th_vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
env->vstart = 0;
return -1LL;
}
+
+enum set_mask_type_th {
+ ONLY_FIRST = 1,
+ INCLUDE_FIRST,
+ BEFORE_FIRST,
+};
+
+static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc, enum set_mask_type_th type)
+{
+ uint32_t mlen = th_mlen(desc);
+ uint32_t vlmax = (env_archcpu(env)->cfg.vlenb << 3) / mlen;
+ uint32_t vm = th_vm(desc);
+ uint32_t vl = env->vl;
+ int i;
+ bool first_mask_bit = false;
+
+ for (i = env->vstart; i < vl; i++) {
+ if (!vm && !th_elem_mask(v0, mlen, i)) {
+ continue;
+ }
+ /* write a zero to all following active elements */
+ if (first_mask_bit) {
+ th_set_elem_mask(vd, mlen, i, 0);
+ continue;
+ }
+ if (th_elem_mask(vs2, mlen, i)) {
+ first_mask_bit = true;
+ if (type == BEFORE_FIRST) {
+ th_set_elem_mask(vd, mlen, i, 0);
+ } else {
+ th_set_elem_mask(vd, mlen, i, 1);
+ }
+ } else {
+ if (type == ONLY_FIRST) {
+ th_set_elem_mask(vd, mlen, i, 0);
+ } else {
+ th_set_elem_mask(vd, mlen, i, 1);
+ }
+ }
+ }
+ env->vstart = 0;
+ for (; i < vlmax; i++) {
+ th_set_elem_mask(vd, mlen, i, 0);
+ }
+}
+
+void HELPER(th_vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
+{
+ vmsetm(vd, v0, vs2, env, desc, BEFORE_FIRST);
+}
+
+void HELPER(th_vmsif_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
+{
+ vmsetm(vd, v0, vs2, env, desc, INCLUDE_FIRST);
+}
+
+void HELPER(th_vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
+{
+ vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST);
+}
--
2.44.0
next prev parent reply other threads:[~2024-04-12 9:50 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 7:36 [PATCH 00/65]target/riscv: Support XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation Huang Tao
2024-04-12 7:36 ` [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs Huang Tao
2024-04-12 7:36 ` [PATCH 03/65] target/riscv: Add properties for XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 05/65] target/riscv: Add mlen in DisasContext Huang Tao
2024-04-12 7:36 ` [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 07/65] target/riscv: implement th.vsetvl{i} " Huang Tao
2024-04-12 7:36 ` [PATCH 08/65] target/riscv: Add strided load instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 09/65] target/riscv: Add strided store " Huang Tao
2024-04-12 7:36 ` [PATCH 10/65] target/riscv: Add unit-stride load " Huang Tao
2024-04-12 7:36 ` [PATCH 11/65] target/riscv: Add unit-stride store " Huang Tao
2024-04-12 7:36 ` [PATCH 12/65] target/riscv: Add indexed load " Huang Tao
2024-04-12 7:36 ` [PATCH 13/65] target/riscv: Add indexed store " Huang Tao
2024-04-12 7:36 ` [PATCH 14/65] target/riscv: Add unit-stride fault-only-first " Huang Tao
2024-04-12 7:36 ` [PATCH 15/65] target/riscv: Add vector amo operations " Huang Tao
2024-04-12 7:36 ` [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 17/65] target/riscv: Add widening integer add/subtract " Huang Tao
2024-04-12 7:36 ` [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow " Huang Tao
2024-04-12 7:36 ` [PATCH 19/65] target/riscv: Add bitwise logical " Huang Tao
2024-04-12 7:36 ` [PATCH 20/65] target/riscv: Add single-width bit shift " Huang Tao
2024-04-12 7:36 ` [PATCH 21/65] target/riscv: Add narrowing integer right " Huang Tao
2024-04-12 7:36 ` [PATCH 22/65] target/riscv: Add integer compare " Huang Tao
2024-04-12 7:36 ` [PATCH 23/65] target/riscv: Add integer min/max " Huang Tao
2024-04-12 7:36 ` [PATCH 24/65] target/riscv: Add single-width integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 25/65] target/riscv: Add integer divide " Huang Tao
2024-04-12 7:36 ` [PATCH 26/65] target/riscv: Add widening integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 27/65] target/riscv: Add single-width integer multiply-add " Huang Tao
2024-04-12 7:36 ` [PATCH 28/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:36 ` [PATCH 29/65] target/riscv: Add integer merge and move " Huang Tao
2024-04-12 7:37 ` [PATCH 30/65] target/riscv: Add single-width saturating add and sub " Huang Tao
2024-04-12 7:37 ` [PATCH 31/65] target/riscv: Add single-width average " Huang Tao
2024-04-12 7:37 ` [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation " Huang Tao
2024-04-12 7:37 ` [PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 34/65] target/riscv: Add single-width scaling shift " Huang Tao
2024-04-12 7:37 ` [PATCH 35/65] target/riscv: Add narrowing fixed-point clip " Huang Tao
2024-04-12 7:37 ` [PATCH 36/65] target/riscv: Add single-width floating-point add/sub " Huang Tao
2024-04-12 7:37 ` [PATCH 37/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide " Huang Tao
2024-04-12 7:37 ` [PATCH 39/65] target/riscv: Add widening floating-point multiply " Huang Tao
2024-04-12 7:37 ` [PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add " Huang Tao
2024-04-12 7:37 ` [PATCH 41/65] target/riscv: Add widening floating-point fused mul-add " Huang Tao
2024-04-12 7:37 ` [PATCH 42/65] target/riscv: Add floating-pointing square-root " Huang Tao
2024-04-12 7:37 ` [PATCH 43/65] target/riscv: Add floating-point MIN/MAX " Huang Tao
2024-04-12 7:37 ` [PATCH 44/65] target/riscv: Add floating-point sign-injection " Huang Tao
2024-04-12 7:37 ` [PATCH 45/65] target/riscv: Add floating-point compare " Huang Tao
2024-04-12 7:37 ` [PATCH 46/65] target/riscv: Add floating-point classify and merge " Huang Tao
2024-04-12 7:37 ` [PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert " Huang Tao
2024-04-12 7:37 ` [PATCH 48/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 49/65] target/riscv: Add narrowing " Huang Tao
2024-04-12 7:37 ` [PATCH 50/65] target/riscv: Add single-width integer reduction " Huang Tao
2024-04-12 7:37 ` [PATCH 51/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 52/65] target/riscv: Add single-width floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 53/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 54/65] target/riscv: Add mask-register logical " Huang Tao
2024-04-12 7:37 ` [PATCH 55/65] target/riscv: Add vector mask population count vmpopc " Huang Tao
2024-04-12 7:37 ` [PATCH 56/65] target/riscv: Add th.vmfirst.m " Huang Tao
2024-04-12 7:37 ` Huang Tao [this message]
2024-04-12 7:37 ` [PATCH 58/65] target/riscv: Add vector iota instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 59/65] target/riscv: Add vector element index " Huang Tao
2024-04-12 7:37 ` [PATCH 60/65] target/riscv: Add integer extract and scalar move instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 61/65] target/riscv: Add floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 62/65] target/riscv: Add vector slide " Huang Tao
2024-04-12 7:37 ` [PATCH 63/65] target/riscv: Add vector register gather " Huang Tao
2024-04-12 7:37 ` [PATCH 64/65] target/riscv: Add vector compress instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 65/65] target/riscv: Enable XTheadVector extension for c906 Huang Tao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240412073735.76413-58-eric.huang@linux.alibaba.com \
--to=eric.huang@linux.alibaba.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).