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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id cs18-20020a056000089200b003437799a373sm5108718wrb.83.2024.04.19.11.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 11:46:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/3] target/arm: Make the counter frequency default 1GHz for new CPUs, machines Date: Fri, 19 Apr 2024 19:46:05 +0100 Message-Id: <20240419184608.2675213-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In previous versions of the Arm architecture, the frequency of the generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value, and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns. In Armv8.6, the architecture standardized this frequency to 1GHz. Because there is no ID register feature field that indicates whether a CPU is v8.6 or that it ought to have this counter frequency, we implement this by changing our default CNTFRQ value for all CPUs, with exceptions for backwards compatibility: * CPU types which we already implement will retain the old default value. None of these are v8.6 CPUs, so this is architecturally OK. * CPUs used in versioned machine types with a version of 9.0 or earlier will retain the old default value. The upshot is that the only CPU type that changes is 'max'; but any new type we add in future (whether v8.6 or not) will also get the new 1GHz default (assuming we spot in code review any attempts to set the ARM_FEATURE_BACKCOMPAT_CNTFRQ flag on new CPU types as a result of cut-n-paste from an older CPU initfn ;-)). It remains the case that the machine model can override the default value via the 'cntfrq' QOM property (regardless of the CPU type). Patch 1 is Paolo's "add the new versioned machine types" patch that he sent out last month; patch 2 is some preliminary cleanup so that we set the default cntfrq value in exactly one place, and patch 3 is the mechanics to set the default appropriately for the two back-compat scenarios. thanks -- PMM Paolo Bonzini (1): hw: Add compat machines for 9.1 Peter Maydell (2): target/arm: Refactor default generic timer frequency handling target/arm: Default to 1GHz cntfrq for 'max' and new CPUs include/hw/boards.h | 3 +++ include/hw/i386/pc.h | 3 +++ target/arm/cpu.h | 11 +++++++++ target/arm/internals.h | 15 +++++++++--- hw/arm/virt.c | 11 +++++++-- hw/core/machine.c | 5 ++++ hw/i386/pc.c | 3 +++ hw/i386/pc_piix.c | 17 +++++++++++--- hw/i386/pc_q35.c | 14 ++++++++++-- hw/m68k/virt.c | 11 +++++++-- hw/ppc/spapr.c | 17 +++++++++++--- hw/s390x/s390-virtio-ccw.c | 14 +++++++++++- target/arm/cpu.c | 47 ++++++++++++++++++++++++++------------ target/arm/cpu64.c | 2 ++ target/arm/helper.c | 16 ++++++------- target/arm/tcg/cpu32.c | 4 ++++ target/arm/tcg/cpu64.c | 18 +++++++++++++++ 17 files changed, 173 insertions(+), 38 deletions(-) -- 2.34.1