From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Clément Chigot" <chigot@adacore.com>,
qemu-stable@nongnu.org
Subject: [PATCH] target/arm: Restrict translation disabled alignment check to VMSA
Date: Mon, 22 Apr 2024 10:07:22 -0700 [thread overview]
Message-ID: <20240422170722.117409-1-richard.henderson@linaro.org> (raw)
For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable.
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
Reported-by: Clément Chigot <chigot@adacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Since v9 will likely be tagged tomorrow without this fixed,
Cc: qemu-stable@nongnu.org
---
target/arm/tcg/hflags.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
index 5da1b0fc1d..66de30b828 100644
--- a/target/arm/tcg/hflags.c
+++ b/target/arm/tcg/hflags.c
@@ -38,8 +38,16 @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
}
/*
- * If translation is disabled, then the default memory type is
- * Device(-nGnRnE) instead of Normal, which requires that alignment
+ * With PMSA, when the MPU is disabled, all memory types in the
+ * default map is Normal.
+ */
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
+ return false;
+ }
+
+ /*
+ * With VMSA, if translation is disabled, then the default memory type
+ * is Device(-nGnRnE) instead of Normal, which requires that alignment
* be enforced. Since this affects all ram, it is most efficient
* to handle this during translation.
*/
--
2.34.1
next reply other threads:[~2024-04-22 17:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-22 17:07 Richard Henderson [this message]
2024-04-22 17:09 ` [PATCH] target/arm: Restrict translation disabled alignment check to VMSA Richard Henderson
2024-04-22 21:02 ` Philippe Mathieu-Daudé
2024-04-23 7:16 ` Clément Chigot
2024-04-25 19:18 ` Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2024-04-24 17:09 [PATCH 0/5] tcg: Misc improvements Richard Henderson
2024-04-24 17:09 ` [PATCH] target/arm: Restrict translation disabled alignment check to VMSA Richard Henderson
2024-05-03 14:58 ` Philippe Mathieu-Daudé
2024-05-03 14:59 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240422170722.117409-1-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=chigot@adacore.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-stable@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).