From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 20/45] target/hppa: Use TCG_COND_TST* in do_cond
Date: Wed, 24 Apr 2024 16:59:58 -0700 [thread overview]
Message-ID: <20240425000023.1002026-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240425000023.1002026-1-richard.henderson@linaro.org>
We can directly test bits of a 32-bit comparison without
zero or sign-extending an intermediate result.
We can directly test bit 0 for odd/even.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 64 ++++++++++++++++++-----------------------
1 file changed, 28 insertions(+), 36 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index a1132c884f..85941f191f 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -774,28 +774,36 @@ static bool cond_need_cb(int c)
static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv)
{
+ TCGCond sign_cond, zero_cond;
+ uint64_t sign_imm, zero_imm;
DisasCond cond;
TCGv_i64 tmp;
+ if (d) {
+ /* 64-bit condition. */
+ sign_imm = 0;
+ sign_cond = TCG_COND_LT;
+ zero_imm = 0;
+ zero_cond = TCG_COND_EQ;
+ } else {
+ /* 32-bit condition. */
+ sign_imm = 1ull << 31;
+ sign_cond = TCG_COND_TSTNE;
+ zero_imm = UINT32_MAX;
+ zero_cond = TCG_COND_TSTEQ;
+ }
+
switch (cf >> 1) {
case 0: /* Never / TR (0 / 1) */
cond = cond_make_f();
break;
case 1: /* = / <> (Z / !Z) */
- if (!d) {
- tmp = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(tmp, res);
- res = tmp;
- }
- cond = cond_make_vi(TCG_COND_EQ, res, 0);
+ cond = cond_make_vi(zero_cond, res, zero_imm);
break;
case 2: /* < / >= (N ^ V / !(N ^ V) */
tmp = tcg_temp_new_i64();
tcg_gen_xor_i64(tmp, res, sv);
- if (!d) {
- tcg_gen_ext32s_i64(tmp, tmp);
- }
- cond = cond_make_ti(TCG_COND_LT, tmp, 0);
+ cond = cond_make_ti(sign_cond, tmp, sign_imm);
break;
case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
/*
@@ -803,21 +811,15 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
* (N ^ V) | Z
* ((res < 0) ^ (sv < 0)) | !res
* ((res ^ sv) < 0) | !res
- * (~(res ^ sv) >= 0) | !res
- * !(~(res ^ sv) >> 31) | !res
- * !(~(res ^ sv) >> 31 & res)
+ * ((res ^ sv) < 0 ? 1 : !res)
+ * !((res ^ sv) < 0 ? 0 : res)
*/
tmp = tcg_temp_new_i64();
- tcg_gen_eqv_i64(tmp, res, sv);
- if (!d) {
- tcg_gen_sextract_i64(tmp, tmp, 31, 1);
- tcg_gen_and_i64(tmp, tmp, res);
- tcg_gen_ext32u_i64(tmp, tmp);
- } else {
- tcg_gen_sari_i64(tmp, tmp, 63);
- tcg_gen_and_i64(tmp, tmp, res);
- }
- cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
+ tcg_gen_xor_i64(tmp, res, sv);
+ tcg_gen_movcond_i64(sign_cond, tmp,
+ tmp, tcg_constant_i64(sign_imm),
+ ctx->zero, res);
+ cond = cond_make_ti(zero_cond, tmp, zero_imm);
break;
case 4: /* NUV / UV (!UV / UV) */
cond = cond_make_vi(TCG_COND_EQ, uv, 0);
@@ -825,23 +827,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */
tmp = tcg_temp_new_i64();
tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res);
- if (!d) {
- tcg_gen_ext32u_i64(tmp, tmp);
- }
- cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
+ cond = cond_make_ti(zero_cond, tmp, zero_imm);
break;
case 6: /* SV / NSV (V / !V) */
- if (!d) {
- tmp = tcg_temp_new_i64();
- tcg_gen_ext32s_i64(tmp, sv);
- sv = tmp;
- }
- cond = cond_make_ti(TCG_COND_LT, sv, 0);
+ cond = cond_make_vi(sign_cond, sv, sign_imm);
break;
case 7: /* OD / EV */
- tmp = tcg_temp_new_i64();
- tcg_gen_andi_i64(tmp, res, 1);
- cond = cond_make_ti(TCG_COND_NE, tmp, 0);
+ cond = cond_make_vi(TCG_COND_TSTNE, res, 1);
break;
default:
g_assert_not_reached();
--
2.34.1
next prev parent reply other threads:[~2024-04-25 0:01 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-24 23:59 [PATCH 00/45] target/hppa: Misc improvements Richard Henderson
2024-04-24 23:59 ` [PATCH 01/45] target/hppa: Move cpu_get_tb_cpu_state out of line Richard Henderson
2024-04-24 23:59 ` [PATCH 02/45] target/hppa: Use hppa_form_gva_psw in hppa_cpu_get_pc Richard Henderson
2024-04-24 23:59 ` [PATCH 03/45] target/hppa: Move constant destination check into use_goto_tb Richard Henderson
2024-04-24 23:59 ` [PATCH 04/45] target/hppa: Pass displacement to do_dbranch Richard Henderson
2024-05-13 11:41 ` Philippe Mathieu-Daudé
2024-04-24 23:59 ` [PATCH 05/45] target/hppa: Allow prior nullification in do_ibranch Richard Henderson
2024-04-24 23:59 ` [PATCH 06/45] target/hppa: Use CF_BP_PAGE instead of cpu_breakpoint_test Richard Henderson
2024-04-24 23:59 ` [PATCH 07/45] target/hppa: Add install_iaq_entries Richard Henderson
2024-04-24 23:59 ` [PATCH 08/45] target/hppa: Add install_link Richard Henderson
2024-04-24 23:59 ` [PATCH 09/45] target/hppa: Delay computation of IAQ_Next Richard Henderson
2024-04-24 23:59 ` [PATCH 10/45] target/hppa: Skip nullified insns in unconditional dbranch path Richard Henderson
2024-04-24 23:59 ` [PATCH 11/45] target/hppa: Simplify TB end Richard Henderson
2024-04-24 23:59 ` [PATCH 12/45] target/hppa: Add IASQ entries to DisasContext Richard Henderson
2024-04-24 23:59 ` [PATCH 13/45] target/hppa: Add space arguments to install_iaq_entries Richard Henderson
2024-04-24 23:59 ` [PATCH 14/45] target/hppa: Add space argument to do_ibranch Richard Henderson
2024-04-24 23:59 ` [PATCH 15/45] target/hppa: Use umax in do_ibranch_priv Richard Henderson
2024-04-24 23:59 ` [PATCH 16/45] target/hppa: Always make a copy " Richard Henderson
2024-04-24 23:59 ` [PATCH 17/45] target/hppa: Introduce and use DisasIAQE for branch management Richard Henderson
2024-04-24 23:59 ` [PATCH 18/45] target/hppa: Use displacements in DisasIAQE Richard Henderson
2024-04-24 23:59 ` [PATCH 19/45] target/hppa: Rename cond_make_* helpers Richard Henderson
2024-04-24 23:59 ` Richard Henderson [this message]
2024-04-24 23:59 ` [PATCH 21/45] target/hppa: Use TCG_COND_TST* in do_log_cond Richard Henderson
2024-04-25 0:00 ` [PATCH 22/45] target/hppa: Use TCG_COND_TST* in do_unit_zero_cond Richard Henderson
2024-04-25 0:00 ` [PATCH 23/45] target/hppa: Use TCG_COND_TST* in do_unit_addsub Richard Henderson
2024-04-25 0:00 ` [PATCH 24/45] target/hppa: Use TCG_COND_TST* in trans_bb_imm Richard Henderson
2024-04-25 0:00 ` [PATCH 25/45] target/hppa: Use registerfields.h for FPSR Richard Henderson
2024-04-25 0:00 ` [PATCH 26/45] target/hppa: Use TCG_COND_TST* in trans_ftest Richard Henderson
2024-04-25 0:00 ` [PATCH 27/45] target/hppa: Remove cond_free Richard Henderson
2024-04-25 0:00 ` [PATCH 28/45] target/hppa: Introduce DisasDelayException Richard Henderson
2024-04-25 0:00 ` [PATCH 29/45] target/hppa: Use delay_excp for conditional traps Richard Henderson
2024-04-25 0:00 ` [PATCH 30/45] target/hppa: Use delay_excp for conditional trap on overflow Richard Henderson
2024-04-25 0:00 ` [PATCH 31/45] linux-user/hppa: Force all code addresses to PRIV_USER Richard Henderson
2024-04-25 0:00 ` [PATCH 32/45] target/hppa: Store full iaoq_f and page bits of iaoq_d in TB Richard Henderson
2024-04-25 0:00 ` [PATCH 33/45] target/hppa: Do not mask in copy_iaoq_entry Richard Henderson
2024-04-25 0:00 ` [PATCH 34/45] target/hppa: Improve hppa_cpu_dump_state Richard Henderson
2024-04-25 0:00 ` [PATCH 35/45] target/hppa: Split PSW X and B into their own field Richard Henderson
2024-04-25 0:00 ` [PATCH 36/45] target/hppa: Manage PSW_X and PSW_B in translator Richard Henderson
2024-04-25 0:00 ` [PATCH 37/45] target/hppa: Implement PSW_B Richard Henderson
2024-04-25 0:00 ` [PATCH 38/45] target/hppa: Implement PSW_X Richard Henderson
2024-04-25 0:00 ` [PATCH 39/45] target/hppa: Drop tlb_entry return from hppa_get_physical_address Richard Henderson
2024-04-25 0:00 ` [PATCH 40/45] target/hppa: Adjust priv for B,GATE at runtime Richard Henderson
2024-04-25 0:00 ` [PATCH 41/45] target/hppa: Implement CF_PCREL Richard Henderson
2024-04-25 0:00 ` [PATCH 42/45] target/hppa: Implement PSW_T Richard Henderson
2024-04-25 0:00 ` [PATCH 43/45] target/hppa: Implement PSW_H, PSW_L Richard Henderson
2024-04-25 0:00 ` [PATCH 44/45] target/hppa: Log cpu state at interrupt Richard Henderson
2024-04-25 0:00 ` [PATCH 45/45] target/hppa: Log cpu state on return-from-interrupt Richard Henderson
2024-05-10 14:48 ` [PATCH 00/45] target/hppa: Misc improvements Philippe Mathieu-Daudé
2024-05-12 16:08 ` Sven Schnelle
2024-05-13 6:11 ` Helge Deller
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240425000023.1002026-21-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).