From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Yoshinori Sato" <ysato@users.sourceforge.jp>,
"Paul Cercueil" <paul@crapouillou.net>,
"John Paul Adrian Glaubitz" <glaubitz@physik.fu-berlin.de>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
qemu-stable@nongnu.org
Subject: [PATCH v3 1/4] target/sh4: Fix ADDV opcode
Date: Tue, 30 Apr 2024 16:56:11 +0200 [thread overview]
Message-ID: <20240430145614.76475-2-philmd@linaro.org> (raw)
In-Reply-To: <20240430145614.76475-1-philmd@linaro.org>
The documentation says:
ADDV Rm, Rn Rn + Rm -> Rn, overflow -> T
But QEMU implementation was:
ADDV Rm, Rn Rn + Rm -> Rm, overflow -> T
Fix by filling the correct Rm register.
Add tests provided by Paul Cercueil.
Cc: qemu-stable@nongnu.org
Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG")
Reported-by: Paul Cercueil <paul@crapouillou.net>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2317
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sh4/translate.c | 2 +-
tests/tcg/sh4/test-addv.c | 23 +++++++++++++++++++++++
tests/tcg/sh4/Makefile.target | 3 +++
3 files changed, 27 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/sh4/test-addv.c
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ebb6c901bf..4a1dd0d1f4 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -714,7 +714,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
tcg_gen_andc_i32(cpu_sr_t, t1, t2);
tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31);
- tcg_gen_mov_i32(REG(B7_4), t0);
+ tcg_gen_mov_i32(REG(B11_8), t0);
}
return;
case 0x2009: /* and Rm,Rn */
diff --git a/tests/tcg/sh4/test-addv.c b/tests/tcg/sh4/test-addv.c
new file mode 100644
index 0000000000..54ac77b867
--- /dev/null
+++ b/tests/tcg/sh4/test-addv.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <limits.h>
+
+static void addv(int a, int b, int res, int carry)
+{
+ unsigned int c;
+
+ asm volatile("addv %2,%0\n"
+ "movt %1\n"
+ : "+r"(a), "=r"(c) : "r"(b) :);
+
+ assert(c == carry && a == res);
+}
+
+int main(void)
+{
+ addv(INT_MAX, 1, INT_MIN, 1);
+ addv(INT_MAX - 1, 1, INT_MAX, 0);
+
+ return 0;
+}
diff --git a/tests/tcg/sh4/Makefile.target b/tests/tcg/sh4/Makefile.target
index 4d09291c0c..521b8b0a76 100644
--- a/tests/tcg/sh4/Makefile.target
+++ b/tests/tcg/sh4/Makefile.target
@@ -17,3 +17,6 @@ TESTS += test-macl
test-macw: CFLAGS += -O -g
TESTS += test-macw
+
+test-addv: CFLAGS += -O -g
+TESTS += test-addv
--
2.41.0
next prev parent reply other threads:[~2024-04-30 14:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 14:56 [PATCH v3 0/4] target/sh4: Fix ADDV/SUBV opcodes Philippe Mathieu-Daudé
2024-04-30 14:56 ` Philippe Mathieu-Daudé [this message]
2024-04-30 14:56 ` [PATCH v3 2/4] target/sh4: Fix SUBV opcode Philippe Mathieu-Daudé
2024-04-30 14:56 ` [PATCH v3 3/4] target/sh4: Rename TCGv variables as manual for ADDV opcode Philippe Mathieu-Daudé
2024-04-30 14:56 ` [PATCH v3 4/4] target/sh4: Rename TCGv variables as manual for SUBV opcode Philippe Mathieu-Daudé
2024-04-30 15:42 ` [PATCH v3 0/4] target/sh4: Fix ADDV/SUBV opcodes Richard Henderson
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