From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, zhao1.liu@intel.com
Subject: [PATCH v2 09/25] target/i386: clarify the "reg" argument of functions returning CCPrepare
Date: Mon, 6 May 2024 10:09:41 +0200 [thread overview]
Message-ID: <20240506080957.10005-10-pbonzini@redhat.com> (raw)
In-Reply-To: <20240506080957.10005-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 2cd7868d596..7efd12cbe7e 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -937,7 +937,7 @@ static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp size)
}
}
-/* compute eflags.C to reg */
+/* compute eflags.C, trying to store it in reg if not NULL */
static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
{
MemOp size;
@@ -1008,7 +1008,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
}
}
-/* compute eflags.P to reg */
+/* compute eflags.P, trying to store it in reg if not NULL */
static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg)
{
gen_compute_eflags(s);
@@ -1016,7 +1016,7 @@ static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg)
.imm = CC_P };
}
-/* compute eflags.S to reg */
+/* compute eflags.S, trying to store it in reg if not NULL */
static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
{
switch (s->cc_op) {
@@ -1040,7 +1040,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
}
}
-/* compute eflags.O to reg */
+/* compute eflags.O, trying to store it in reg if not NULL */
static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
{
switch (s->cc_op) {
@@ -1060,7 +1060,7 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
}
}
-/* compute eflags.Z to reg */
+/* compute eflags.Z, trying to store it in reg if not NULL */
static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
{
switch (s->cc_op) {
@@ -1090,8 +1090,9 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
}
}
-/* perform a conditional store into register 'reg' according to jump opcode
- value 'b'. In the fast case, T0 is guaranteed not to be used. */
+/* return how to compute jump opcode 'b'. 'reg' can be clobbered
+ * if needed; it may be used for CCPrepare.reg if that will
+ * provide more freedom in the translation of a subsequent setcond. */
static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
{
int inv, jcc_op, cond;
--
2.45.0
next prev parent reply other threads:[~2024-05-06 8:15 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 8:09 [PATCH v2 00/25] target/i386: convert 1-byte opcodes to new decoder Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 01/25] target/i386: use TSTEQ/TSTNE to test low bits Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 02/25] target/i386: use TSTEQ/TSTNE to check flags Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 03/25] target/i386: remove mask from CCPrepare Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 04/25] target/i386: cc_op is not dynamic in gen_jcc1 Paolo Bonzini
2024-05-06 15:53 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 05/25] target/i386: cleanup cc_op changes for REP/REPZ/REPNZ Paolo Bonzini
2024-05-06 16:07 ` Richard Henderson
2024-05-06 16:31 ` Paolo Bonzini
2024-05-06 16:39 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 06/25] target/i386: pull cc_op update to callers of gen_jmp_rel{, _csize} Paolo Bonzini
2024-05-06 16:12 ` [PATCH v2 06/25] target/i386: pull cc_op update to callers of gen_jmp_rel{,_csize} Richard Henderson
2024-05-06 8:09 ` [PATCH v2 07/25] target/i386: extend cc_* when using them to compute flags Paolo Bonzini
2024-05-06 16:16 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 08/25] target/i386: do not use s->T0 and s->T1 as scratch registers for CCPrepare Paolo Bonzini
2024-05-06 16:18 ` Richard Henderson
2024-05-06 8:09 ` Paolo Bonzini [this message]
2024-05-06 16:19 ` [PATCH v2 09/25] target/i386: clarify the "reg" argument of functions returning CCPrepare Richard Henderson
2024-05-06 8:09 ` [PATCH v2 10/25] target/i386: cleanup *gen_eob* Paolo Bonzini
2024-05-06 16:21 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 11/25] target/i386: reintroduce debugging mechanism Paolo Bonzini
2024-05-06 16:23 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 12/25] target/i386: move 00-5F opcodes to new decoder Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 13/25] target/i386: extract gen_far_call/jmp, reordering temporaries Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 14/25] target/i386: allow instructions with more than one immediate Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 15/25] target/i386: move 60-BF opcodes to new decoder Paolo Bonzini
2024-05-06 16:44 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 16/25] target/i386: generalize gen_movl_seg_T0 Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 17/25] target/i386: move C0-FF opcodes to new decoder (except for x87) Paolo Bonzini
2024-05-06 16:56 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 18/25] target/i386: merge and enlarge a few ranges for call to disas_insn_new Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 19/25] target/i386: move remaining conditional operations to new decoder Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 20/25] target/i386: move BSWAP " Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 21/25] target/i386: port extensions of one-byte opcodes " Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 22/25] target/i386: remove now-converted opcodes from old decoder Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 23/25] target/i386: decode x87 instructions in a separate function Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 24/25] target/i386: split legacy decoder into " Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 25/25] target/i386: remove duplicate prefix decoding Paolo Bonzini
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