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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41f87c2544esm89783845e9.16.2024.05.10.01.29.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 01:29:51 -0700 (PDT) Date: Fri, 10 May 2024 10:29:50 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: Rob Bradford , qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" Subject: Re: [PATCH] target/riscv: Remove experimental prefix from "B" extension Message-ID: <20240510-bd3888b24a94d2a7cbbb9b96@orel> References: <20240507102721.55845-1-rbradford@rivosinc.com> <20240508-ff6bfb7f94499a3a8d6382f6@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, May 09, 2024 at 02:23:42PM GMT, Daniel Henrique Barboza wrote: > > > On 5/8/24 08:22, Andrew Jones wrote: > > On Tue, May 07, 2024 at 11:27:21AM GMT, Rob Bradford wrote: > > > This extension has now been ratified: > > > https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be > > > removed. > > > > > > Signed-off-by: Rob Bradford > > > --- > > > target/riscv/cpu.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index eb1a2e7d6d..861d9f4350 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -1396,7 +1396,7 @@ static const MISAExtInfo misa_ext_info_arr[] = { > > > MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), > > > MISA_EXT_INFO(RVV, "v", "Vector operations"), > > > MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), > > > - MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") > > > + MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)") > > > }; > > > static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) > > > -- > > > 2.44.0 > > > > > > > > > > Reviewed-by: Andrew Jones > > > > I think we should also either change the false to true for RVB in > > misa_ext_cfgs[] or at least ensure RVB is set for the 'max' cpu > > type in riscv_init_max_cpu_extensions(). > > I prefer if we keep misa_ext_cfgs[] as is. Changing the defaults in this array > will also change the defaults for rv64. IMO we should enable RVB manually in > riscv_init_max_cpu_extensions(). > > We already have some precedence for it: RVV is enabled in 'max' while is default > 'false' for rv64. But do we care if rv64 gets B? rv64 doesn't have any particular set of extensions, afaik. And B seems like it should be generally adopted enough to be in a "general" cpu type like rv64. Anyway, either way works for me as long as 'max' gets B one way or another. Thanks, drew