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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0bf31a7asm25579175ad.140.2024.05.09.23.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 23:53:18 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Fea.Wang" Subject: [PATCH 0/5] target/riscv: Support RISC-V privilege 1.13 spec Date: Fri, 10 May 2024 14:58:50 +0800 Message-Id: <20240510065856.2436870-1-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=fea.wang@sifive.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 10 May 2024 09:17:57 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on the change log for the RISC-V privilege 1.13 spec, add the support for ss1p13. Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72 Lists what to do without clarification or document format. * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip, implementation ignored) * Added the constraint that SXLEN≥UXLEN.(Skip, implementation ignored) * Defined the misa.V field to reflect that the V extension has been implemented.(Skip, existed) * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these patches) * Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension..(Skip, implementation ignored) * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed) * Defined hardware error and software check exception codes.(Done in these patches) * Specified synchronization requirements when changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored) * Incorporated Svade and Svadu extension specifications.(Skip, existed) Fea.Wang (4): target/riscv: Support the version for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Reserve exception codes for sw-check and hw-err Jim Shu (1): target/riscv: Reuse the conversion function of priv_spec and string target/riscv/cpu.c | 10 +++++++--- target/riscv/cpu.h | 7 ++++++- target/riscv/cpu_bits.h | 5 +++++ target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 41 ++++++++++++++++++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 17 ++++++++-------- 6 files changed, 69 insertions(+), 12 deletions(-) -- 2.34.1