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* [PATCH v2 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA
@ 2024-05-15  9:11 Yong-Xuan Wang
  2024-05-15 14:34 ` Andrew Jones
  2024-05-27  5:06 ` Alistair Francis
  0 siblings, 2 replies; 3+ messages in thread
From: Yong-Xuan Wang @ 2024-05-15  9:11 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Yong-Xuan Wang,
	Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
	Daniel Henrique Barboza, Liu Zhiwei, Andrew Jones,
	Philippe Mathieu-Daudé

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
Changelog
v2:
- update commit message
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 473416649fda..235e2cdaca1a 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.17.1



^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH v2 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA
  2024-05-15  9:11 [PATCH v2 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA Yong-Xuan Wang
@ 2024-05-15 14:34 ` Andrew Jones
  2024-05-27  5:06 ` Alistair Francis
  1 sibling, 0 replies; 3+ messages in thread
From: Andrew Jones @ 2024-05-15 14:34 UTC (permalink / raw)
  To: Yong-Xuan Wang
  Cc: qemu-devel, qemu-riscv, greentime.hu, vincent.chen, frank.chang,
	jim.shu, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
	Daniel Henrique Barboza, Liu Zhiwei, Philippe Mathieu-Daudé

On Wed, May 15, 2024 at 05:11:28PM GMT, Yong-Xuan Wang wrote:
> In AIA spec, each hart (or each hart within a group) has a unique hart
> number to locate the memory pages of interrupt files in the address
> space. The number of bits required to represent any hart number is equal
> to ceil(log2(hmax + 1)), where hmax is the largest hart number among
> groups.
> 
> However, if the largest hart number among groups is a power of 2, QEMU
> will pass an inaccurate hart-index-bit setting to Linux. For example, when
> the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
> to represent 4 harts, but we passes 3 to Linux. The code needs to be
> updated to ensure accurate hart-index-bit settings.
> 
> Additionally, a Linux patch[1] is necessary to correctly recover the hart
> index when the guest OS has only 1 hart, where the hart-index-bit is 0.
> 
> [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
> 
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> Changelog
> v2:
> - update commit message
> ---
>  target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 473416649fda..235e2cdaca1a 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
>          }
>      }
>  
> -    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
> +
> +    if (max_hart_per_socket > 1) {
> +        max_hart_per_socket--;
> +        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
> +    } else {
> +        hart_bits = 0;
> +    }
> +
>      ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
>                              KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
>                              &hart_bits, true, NULL);
> -- 
> 2.17.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA
  2024-05-15  9:11 [PATCH v2 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA Yong-Xuan Wang
  2024-05-15 14:34 ` Andrew Jones
@ 2024-05-27  5:06 ` Alistair Francis
  1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2024-05-27  5:06 UTC (permalink / raw)
  To: Yong-Xuan Wang
  Cc: qemu-devel, qemu-riscv, greentime.hu, vincent.chen, frank.chang,
	jim.shu, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
	Daniel Henrique Barboza, Liu Zhiwei, Andrew Jones,
	Philippe Mathieu-Daudé

On Wed, May 15, 2024 at 7:12 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
>
> In AIA spec, each hart (or each hart within a group) has a unique hart
> number to locate the memory pages of interrupt files in the address
> space. The number of bits required to represent any hart number is equal
> to ceil(log2(hmax + 1)), where hmax is the largest hart number among
> groups.
>
> However, if the largest hart number among groups is a power of 2, QEMU
> will pass an inaccurate hart-index-bit setting to Linux. For example, when
> the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
> to represent 4 harts, but we passes 3 to Linux. The code needs to be
> updated to ensure accurate hart-index-bit settings.
>
> Additionally, a Linux patch[1] is necessary to correctly recover the hart
> index when the guest OS has only 1 hart, where the hart-index-bit is 0.
>
> [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
> Changelog
> v2:
> - update commit message
> ---
>  target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 473416649fda..235e2cdaca1a 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
>          }
>      }
>
> -    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
> +
> +    if (max_hart_per_socket > 1) {
> +        max_hart_per_socket--;
> +        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
> +    } else {
> +        hart_bits = 0;
> +    }
> +
>      ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
>                              KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
>                              &hart_bits, true, NULL);
> --
> 2.17.1
>
>


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2024-05-27  5:07 UTC | newest]

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2024-05-15  9:11 [PATCH v2 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA Yong-Xuan Wang
2024-05-15 14:34 ` Andrew Jones
2024-05-27  5:06 ` Alistair Francis

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