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[31.30.173.78]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b895731sm16763633f8f.42.2024.05.15.07.34.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 07:34:14 -0700 (PDT) Date: Wed, 15 May 2024 16:34:13 +0200 From: Andrew Jones To: Yong-Xuan Wang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH v2 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA Message-ID: <20240515-aad670c0d802abedcd4a240d@orel> References: <20240515091129.28116-1-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240515091129.28116-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=ajones@ventanamicro.com; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, May 15, 2024 at 05:11:28PM GMT, Yong-Xuan Wang wrote: > In AIA spec, each hart (or each hart within a group) has a unique hart > number to locate the memory pages of interrupt files in the address > space. The number of bits required to represent any hart number is equal > to ceil(log2(hmax + 1)), where hmax is the largest hart number among > groups. > > However, if the largest hart number among groups is a power of 2, QEMU > will pass an inaccurate hart-index-bit setting to Linux. For example, when > the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient > to represent 4 harts, but we passes 3 to Linux. The code needs to be > updated to ensure accurate hart-index-bit settings. > > Additionally, a Linux patch[1] is necessary to correctly recover the hart > index when the guest OS has only 1 hart, where the hart-index-bit is 0. > > [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/ > > Signed-off-by: Yong-Xuan Wang > --- > Changelog > v2: > - update commit message > --- > target/riscv/kvm/kvm-cpu.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 473416649fda..235e2cdaca1a 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, > } > } > > - hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; > + > + if (max_hart_per_socket > 1) { > + max_hart_per_socket--; > + hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; > + } else { > + hart_bits = 0; > + } > + > ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, > &hart_bits, true, NULL); > -- > 2.17.1 > Reviewed-by: Andrew Jones