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[31.30.173.78]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacf89sm15683615f8f.83.2024.05.15.00.16.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 00:16:55 -0700 (PDT) Date: Wed, 15 May 2024 09:16:54 +0200 From: Andrew Jones To: Eric Cheng Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, tjeznach@rivosinc.com Subject: Re: [PATCH v2 06/15] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug Message-ID: <20240515-e56bce8b02b918c106961996@orel> References: <20240307160319.675044-1-dbarboza@ventanamicro.com> <20240307160319.675044-7-dbarboza@ventanamicro.com> <41835d3f-d9e2-4ace-8add-f5bb6c525c5f@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <41835d3f-d9e2-4ace-8add-f5bb6c525c5f@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, May 15, 2024 at 02:25:31PM GMT, Eric Cheng wrote: > On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > > > Generate device tree entry for riscv-iommu PCI device, along with > > mapping all PCI device identifiers to the single IOMMU device instance. > > > > Signed-off-by: Tomasz Jeznach > > Signed-off-by: Daniel Henrique Barboza > > --- > > hw/riscv/virt.c | 33 ++++++++++++++++++++++++++++++++- > > 1 file changed, 32 insertions(+), 1 deletion(-) > > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > > index a094af97c3..67a8267747 100644 > > --- a/hw/riscv/virt.c > > +++ b/hw/riscv/virt.c > > @@ -32,6 +32,7 @@ > > #include "hw/core/sysbus-fdt.h" > > #include "target/riscv/pmu.h" > > #include "hw/riscv/riscv_hart.h" > > +#include "hw/riscv/iommu.h" > > #include "hw/riscv/virt.h" > > #include "hw/riscv/boot.h" > > #include "hw/riscv/numa.h" > > @@ -1004,6 +1005,30 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) > > bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); > > } > > +static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) > > +{ > > + const char comp[] = "riscv,pci-iommu"; > > + void *fdt = MACHINE(s)->fdt; > > + uint32_t iommu_phandle; > > + g_autofree char *iommu_node = NULL; > > + g_autofree char *pci_node = NULL; > > + > > + pci_node = g_strdup_printf("/soc/pci@%lx", > > + (long) virt_memmap[VIRT_PCIE_ECAM].base); > > + iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf); > > + iommu_phandle = qemu_fdt_alloc_phandle(fdt); > > + qemu_fdt_add_subnode(fdt, iommu_node); > > + > > + qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); > > + qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); > > + qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); > > + qemu_fdt_setprop_cells(fdt, iommu_node, "reg", > > + bdf << 8, 0, 0, 0, 0); > > + qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", > > + 0, iommu_phandle, 0, bdf, > > + bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); > > +} > > Is it really necessary to add this iommu-pci device in riscv virt machine, > rather than other 'physical' machine type? virt machine already has its > virtio-iommu. > We need both, just as the Arm virt machine has both. virtio-iommu is for guests, but the Arm and RISCV virt machines are both also used as hosts. Thanks, drew