From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "jasowang@redhat.com" <jasowang@redhat.com>,
"zhenzhong.duan@intel.com" <zhenzhong.duan@intel.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"peterx@redhat.com" <peterx@redhat.com>,
CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
Subject: [PATCH ats_vtd v2 05/25] intel_iommu: return page walk level even when the translation fails
Date: Wed, 15 May 2024 07:14:15 +0000 [thread overview]
Message-ID: <20240515071057.33990-6-clement.mathieu--drif@eviden.com> (raw)
In-Reply-To: <20240515071057.33990-1-clement.mathieu--drif@eviden.com>
We use this information in vtd_do_iommu_translate to populate the
IOMMUTLBEntry and indicate the correct page mask. This prevents ATS
devices from sending many useless translation requests when a megapage
or gigapage iova is not mapped to a physical address.
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
---
hw/i386/intel_iommu.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 252364893b..7a4dd738a3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2064,9 +2064,9 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce,
uint32_t pasid)
{
dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce, pasid);
- uint32_t level = vtd_get_iova_level(s, ce, pasid);
uint32_t offset;
uint64_t flpte;
+ *flpte_level = vtd_get_iova_level(s, ce, pasid);
if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) {
error_report_once("%s: detected non canonical IOVA (iova=0x%" PRIx64 ","
@@ -2075,10 +2075,10 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce,
}
while (true) {
- offset = vtd_iova_fl_level_offset(iova, level);
+ offset = vtd_iova_fl_level_offset(iova, *flpte_level);
flpte = vtd_get_flpte(addr, offset);
if (flpte == (uint64_t)-1) {
- if (level == vtd_get_iova_level(s, ce, pasid)) {
+ if (*flpte_level == vtd_get_iova_level(s, ce, pasid)) {
/* Invalid programming of context-entry */
return -VTD_FR_CONTEXT_ENTRY_INV;
} else {
@@ -2103,19 +2103,18 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce,
return -VTD_FR_FS_BIT_UPDATE_FAILED;
}
- if (vtd_is_last_flpte(flpte, level)) {
+ if (vtd_is_last_flpte(flpte, *flpte_level)) {
if (is_write &&
(vtd_set_flag_in_pte(addr, offset, flpte, VTD_FL_PTE_D) !=
MEMTX_OK)) {
return -VTD_FR_FS_BIT_UPDATE_FAILED;
}
*flptep = flpte;
- *flpte_level = level;
return 0;
}
addr = vtd_get_flpte_addr(flpte, aw_bits);
- level--;
+ (*flpte_level)--;
}
}
--
2.44.0
next prev parent reply other threads:[~2024-05-15 7:18 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 7:14 [PATCH ats_vtd v2 00/25] ATS support for VT-d CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 01/25] intel_iommu: fix FRCD construction macro CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 03/25] intel_iommu: check if the input address is canonical CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 02/25] intel_iommu: make types match CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 07/25] intel_iommu: do not consider wait_desc as an invalid descriptor CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 06/25] intel_iommu: extract device IOTLB invalidation logic CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` CLEMENT MATHIEU--DRIF [this message]
2024-05-15 7:14 ` [PATCH ats_vtd v2 04/25] intel_iommu: set accessed and dirty bits during first stage translation CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 09/25] pcie: add helper to declare PASID capability for a pcie device CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 10/25] pcie: helper functions to check if PASID and ATS are enabled CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 12/25] intel_iommu: add an internal API to find an address space with PASID CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 11/25] intel_iommu: declare supported PASID size CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 08/25] memory: add permissions in IOMMUAccessFlags CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 16/25] pci: add a pci-level initialization function for iommu notifiers CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 15/25] pci: add IOMMU operations to get address spaces and memory regions with PASID CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 14/25] pci: cache the bus mastering status in the device CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 13/25] intel_iommu: add support for PASID-based device IOTLB invalidation CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 18/25] intel_iommu: implement the get_memory_region_pasid iommu operation CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 17/25] intel_iommu: implement the get_address_space_pasid " CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 19/25] memory: Allow to store the PASID in IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 20/25] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2024-05-17 10:40 ` Duan, Zhenzhong
2024-05-17 11:11 ` CLEMENT MATHIEU--DRIF
2024-05-21 3:11 ` Duan, Zhenzhong
2024-05-21 5:09 ` CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 21/25] atc: generic ATC that can be used by PCIe devices that support SVM CLEMENT MATHIEU--DRIF
2024-05-17 10:44 ` Duan, Zhenzhong
2024-05-17 11:12 ` CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 23/25] pci: add a pci-level API for ATS CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 22/25] memory: add an API for ATS support CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 24/25] intel_iommu: set the address mask even when a translation fails CLEMENT MATHIEU--DRIF
2024-05-15 7:14 ` [PATCH ats_vtd v2 25/25] intel_iommu: add support for ATS CLEMENT MATHIEU--DRIF
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