From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Helge Deller <deller@gmx.de>
Subject: [PULL 20/43] target/hppa: Use TCG_COND_TST* in do_cond
Date: Wed, 15 May 2024 11:40:20 +0200 [thread overview]
Message-ID: <20240515094043.82850-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org>
We can directly test bits of a 32-bit comparison without
zero or sign-extending an intermediate result.
We can directly test bit 0 for odd/even.
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 64 ++++++++++++++++++-----------------------
1 file changed, 28 insertions(+), 36 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 07ba35001b..813f1571e9 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -776,28 +776,36 @@ static bool cond_need_cb(int c)
static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv)
{
+ TCGCond sign_cond, zero_cond;
+ uint64_t sign_imm, zero_imm;
DisasCond cond;
TCGv_i64 tmp;
+ if (d) {
+ /* 64-bit condition. */
+ sign_imm = 0;
+ sign_cond = TCG_COND_LT;
+ zero_imm = 0;
+ zero_cond = TCG_COND_EQ;
+ } else {
+ /* 32-bit condition. */
+ sign_imm = 1ull << 31;
+ sign_cond = TCG_COND_TSTNE;
+ zero_imm = UINT32_MAX;
+ zero_cond = TCG_COND_TSTEQ;
+ }
+
switch (cf >> 1) {
case 0: /* Never / TR (0 / 1) */
cond = cond_make_f();
break;
case 1: /* = / <> (Z / !Z) */
- if (!d) {
- tmp = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(tmp, res);
- res = tmp;
- }
- cond = cond_make_vi(TCG_COND_EQ, res, 0);
+ cond = cond_make_vi(zero_cond, res, zero_imm);
break;
case 2: /* < / >= (N ^ V / !(N ^ V) */
tmp = tcg_temp_new_i64();
tcg_gen_xor_i64(tmp, res, sv);
- if (!d) {
- tcg_gen_ext32s_i64(tmp, tmp);
- }
- cond = cond_make_ti(TCG_COND_LT, tmp, 0);
+ cond = cond_make_ti(sign_cond, tmp, sign_imm);
break;
case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
/*
@@ -805,21 +813,15 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
* (N ^ V) | Z
* ((res < 0) ^ (sv < 0)) | !res
* ((res ^ sv) < 0) | !res
- * (~(res ^ sv) >= 0) | !res
- * !(~(res ^ sv) >> 31) | !res
- * !(~(res ^ sv) >> 31 & res)
+ * ((res ^ sv) < 0 ? 1 : !res)
+ * !((res ^ sv) < 0 ? 0 : res)
*/
tmp = tcg_temp_new_i64();
- tcg_gen_eqv_i64(tmp, res, sv);
- if (!d) {
- tcg_gen_sextract_i64(tmp, tmp, 31, 1);
- tcg_gen_and_i64(tmp, tmp, res);
- tcg_gen_ext32u_i64(tmp, tmp);
- } else {
- tcg_gen_sari_i64(tmp, tmp, 63);
- tcg_gen_and_i64(tmp, tmp, res);
- }
- cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
+ tcg_gen_xor_i64(tmp, res, sv);
+ tcg_gen_movcond_i64(sign_cond, tmp,
+ tmp, tcg_constant_i64(sign_imm),
+ ctx->zero, res);
+ cond = cond_make_ti(zero_cond, tmp, zero_imm);
break;
case 4: /* NUV / UV (!UV / UV) */
cond = cond_make_vi(TCG_COND_EQ, uv, 0);
@@ -827,23 +829,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */
tmp = tcg_temp_new_i64();
tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res);
- if (!d) {
- tcg_gen_ext32u_i64(tmp, tmp);
- }
- cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
+ cond = cond_make_ti(zero_cond, tmp, zero_imm);
break;
case 6: /* SV / NSV (V / !V) */
- if (!d) {
- tmp = tcg_temp_new_i64();
- tcg_gen_ext32s_i64(tmp, sv);
- sv = tmp;
- }
- cond = cond_make_ti(TCG_COND_LT, sv, 0);
+ cond = cond_make_vi(sign_cond, sv, sign_imm);
break;
case 7: /* OD / EV */
- tmp = tcg_temp_new_i64();
- tcg_gen_andi_i64(tmp, res, 1);
- cond = cond_make_ti(TCG_COND_NE, tmp, 0);
+ cond = cond_make_vi(TCG_COND_TSTNE, res, 1);
break;
default:
g_assert_not_reached();
--
2.34.1
next prev parent reply other threads:[~2024-05-15 9:41 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 9:40 [PULL 00/43] target/hppa: Misc improvements Richard Henderson
2024-05-15 9:40 ` [PULL 01/43] target/hppa: Move cpu_get_tb_cpu_state out of line Richard Henderson
2024-05-15 9:40 ` [PULL 02/43] target/hppa: Use hppa_form_gva_psw in hppa_cpu_get_pc Richard Henderson
2024-05-15 9:40 ` [PULL 03/43] target/hppa: Move constant destination check into use_goto_tb Richard Henderson
2024-05-15 9:40 ` [PULL 04/43] target/hppa: Pass displacement to do_dbranch Richard Henderson
2024-05-15 9:40 ` [PULL 05/43] target/hppa: Allow prior nullification in do_ibranch Richard Henderson
2024-05-15 9:40 ` [PULL 06/43] target/hppa: Use CF_BP_PAGE instead of cpu_breakpoint_test Richard Henderson
2024-05-15 9:40 ` [PULL 07/43] target/hppa: Add install_iaq_entries Richard Henderson
2024-05-15 9:40 ` [PULL 08/43] target/hppa: Add install_link Richard Henderson
2024-05-15 9:40 ` [PULL 09/43] target/hppa: Delay computation of IAQ_Next Richard Henderson
2024-05-15 9:40 ` [PULL 10/43] target/hppa: Skip nullified insns in unconditional dbranch path Richard Henderson
2024-05-15 9:40 ` [PULL 11/43] target/hppa: Simplify TB end Richard Henderson
2024-05-15 9:40 ` [PULL 12/43] target/hppa: Add IASQ entries to DisasContext Richard Henderson
2024-05-15 9:40 ` [PULL 13/43] target/hppa: Add space arguments to install_iaq_entries Richard Henderson
2024-05-15 9:40 ` [PULL 14/43] target/hppa: Add space argument to do_ibranch Richard Henderson
2024-05-15 9:40 ` [PULL 15/43] target/hppa: Use umax in do_ibranch_priv Richard Henderson
2024-05-15 9:40 ` [PULL 16/43] target/hppa: Always make a copy " Richard Henderson
2024-05-15 9:40 ` [PULL 17/43] target/hppa: Introduce and use DisasIAQE for branch management Richard Henderson
2024-05-15 9:40 ` [PULL 18/43] target/hppa: Use displacements in DisasIAQE Richard Henderson
2024-05-15 9:40 ` [PULL 19/43] target/hppa: Rename cond_make_* helpers Richard Henderson
2024-05-15 9:40 ` Richard Henderson [this message]
2024-05-15 9:40 ` [PULL 21/43] target/hppa: Use TCG_COND_TST* in do_log_cond Richard Henderson
2024-05-15 9:40 ` [PULL 22/43] target/hppa: Use TCG_COND_TST* in do_unit_zero_cond Richard Henderson
2024-05-15 9:40 ` [PULL 23/43] target/hppa: Use TCG_COND_TST* in do_unit_addsub Richard Henderson
2024-05-15 9:40 ` [PULL 24/43] target/hppa: Use TCG_COND_TST* in trans_bb_imm Richard Henderson
2024-05-15 9:40 ` [PULL 25/43] target/hppa: Use registerfields.h for FPSR Richard Henderson
2024-05-15 9:40 ` [PULL 26/43] target/hppa: Use TCG_COND_TST* in trans_ftest Richard Henderson
2024-05-15 9:40 ` [PULL 27/43] target/hppa: Remove cond_free Richard Henderson
2024-05-15 9:40 ` [PULL 28/43] target/hppa: Introduce DisasDelayException Richard Henderson
2024-05-15 9:40 ` [PULL 29/43] target/hppa: Use delay_excp for conditional traps Richard Henderson
2024-05-15 9:40 ` [PULL 30/43] target/hppa: Use delay_excp for conditional trap on overflow Richard Henderson
2024-05-15 9:40 ` [PULL 31/43] linux-user/hppa: Force all code addresses to PRIV_USER Richard Henderson
2024-05-15 9:40 ` [PULL 32/43] target/hppa: Store full iaoq_f and page offset of iaoq_b in TB Richard Henderson
2024-05-15 9:40 ` [PULL 33/43] target/hppa: Do not mask in copy_iaoq_entry Richard Henderson
2024-05-15 9:40 ` [PULL 34/43] target/hppa: Improve hppa_cpu_dump_state Richard Henderson
2024-05-15 9:40 ` [PULL 35/43] target/hppa: Split PSW X and B into their own field Richard Henderson
2024-05-15 9:40 ` [PULL 36/43] target/hppa: Manage PSW_X and PSW_B in translator Richard Henderson
2024-05-15 9:40 ` [PULL 37/43] target/hppa: Implement PSW_B Richard Henderson
2024-05-15 9:40 ` [PULL 38/43] target/hppa: Implement PSW_X Richard Henderson
2024-05-15 9:40 ` [PULL 39/43] target/hppa: Drop tlb_entry return from hppa_get_physical_address Richard Henderson
2024-05-15 9:40 ` [PULL 40/43] target/hppa: Adjust priv for B,GATE at runtime Richard Henderson
2024-05-15 9:40 ` [PULL 41/43] target/hppa: Implement CF_PCREL Richard Henderson
2024-05-15 9:40 ` [PULL 42/43] target/hppa: Log cpu state at interrupt Richard Henderson
2024-05-15 9:40 ` [PULL 43/43] target/hppa: Log cpu state on return-from-interrupt Richard Henderson
2024-05-15 12:59 ` [PULL 00/43] target/hppa: Misc improvements Richard Henderson
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