* [PULL 1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec
2024-05-23 16:15 [PULL 0/5] tcg patch queue Richard Henderson
@ 2024-05-23 16:15 ` Richard Henderson
2024-05-23 16:15 ` [PULL 2/5] tcg: Expand TCG_COND_TST* if not TCG_TARGET_HAS_tst_vec Richard Henderson
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2024-05-23 16:15 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Prelude to supporting TCG_COND_TST* in vector comparisons.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 1 +
tcg/aarch64/tcg-target.h | 1 +
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target.h | 1 +
tcg/loongarch64/tcg-target.h | 1 +
tcg/ppc/tcg-target.h | 1 +
tcg/s390x/tcg-target.h | 1 +
7 files changed, 7 insertions(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 2a1c080bab..21d5884741 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -155,6 +155,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
+#define TCG_TARGET_HAS_tst_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 85d5746e47..138bafb9da 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -167,6 +167,7 @@ typedef enum {
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
+#define TCG_TARGET_HAS_tst_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index a43875cb09..434a892e07 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -150,6 +150,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
+#define TCG_TARGET_HAS_tst_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index a10d4e1fce..2f67a97e05 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -224,6 +224,7 @@ typedef enum {
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec have_avx512vl
#define TCG_TARGET_HAS_cmpsel_vec -1
+#define TCG_TARGET_HAS_tst_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index fede627bf7..29e4860d20 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -194,6 +194,7 @@ typedef enum {
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
+#define TCG_TARGET_HAS_tst_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 04a7aba4d3..e154fb14df 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -173,6 +173,7 @@ typedef enum {
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec have_vsx
#define TCG_TARGET_HAS_cmpsel_vec 0
+#define TCG_TARGET_HAS_tst_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index ae448c3a3a..62ce9d792a 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -163,6 +163,7 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
+#define TCG_TARGET_HAS_tst_vec 0
/* used for function call generation */
#define TCG_TARGET_STACK_ALIGN 8
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PULL 2/5] tcg: Expand TCG_COND_TST* if not TCG_TARGET_HAS_tst_vec
2024-05-23 16:15 [PULL 0/5] tcg patch queue Richard Henderson
2024-05-23 16:15 ` [PULL 1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec Richard Henderson
@ 2024-05-23 16:15 ` Richard Henderson
2024-05-23 16:15 ` [PULL 3/5] tcg/aarch64: Support TCG_TARGET_HAS_tst_vec Richard Henderson
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2024-05-23 16:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op-vec.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 094298bb27..84af210bc0 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -508,9 +508,11 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
TCGTemp *rt = tcgv_vec_temp(r);
TCGTemp *at = tcgv_vec_temp(a);
TCGTemp *bt = tcgv_vec_temp(b);
+ TCGTemp *tt = NULL;
TCGArg ri = temp_arg(rt);
TCGArg ai = temp_arg(at);
TCGArg bi = temp_arg(bt);
+ TCGArg ti;
TCGType type = rt->base_type;
int can;
@@ -518,6 +520,18 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
tcg_debug_assert(bt->base_type >= type);
tcg_assert_listed_vecop(INDEX_op_cmp_vec);
can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
+
+ if (!TCG_TARGET_HAS_tst_vec && is_tst_cond(cond)) {
+ tt = tcg_temp_new_internal(type, TEMP_EBB);
+ ti = temp_arg(tt);
+ vec_gen_3(INDEX_op_and_vec, type, 0, ti, ai, bi);
+ at = tt;
+ ai = ti;
+ bt = tcg_constant_internal(type, 0);
+ bi = temp_arg(bt);
+ cond = tcg_tst_eqne_cond(cond);
+ }
+
if (can > 0) {
vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
} else {
@@ -526,6 +540,10 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
tcg_swap_vecop_list(hold_list);
}
+
+ if (tt) {
+ tcg_temp_free_internal(tt);
+ }
}
static bool do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PULL 3/5] tcg/aarch64: Support TCG_TARGET_HAS_tst_vec
2024-05-23 16:15 [PULL 0/5] tcg patch queue Richard Henderson
2024-05-23 16:15 ` [PULL 1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec Richard Henderson
2024-05-23 16:15 ` [PULL 2/5] tcg: Expand TCG_COND_TST* if not TCG_TARGET_HAS_tst_vec Richard Henderson
@ 2024-05-23 16:15 ` Richard Henderson
2024-05-23 16:15 ` [PULL 4/5] tcg/arm: " Richard Henderson
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2024-05-23 16:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/aarch64/tcg-target.c.inc | 26 ++++++++++++++++++++++++--
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 138bafb9da..8bd9e6a5eb 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -167,7 +167,7 @@ typedef enum {
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
-#define TCG_TARGET_HAS_tst_vec 0
+#define TCG_TARGET_HAS_tst_vec 1
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 56fc9cb9e0..ffa8a3e519 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2737,7 +2737,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
TCGCond cond = args[3];
AArch64Insn insn;
- if (cond == TCG_COND_NE) {
+ switch (cond) {
+ case TCG_COND_NE:
if (const_args[2]) {
if (is_scalar) {
tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);
@@ -2752,7 +2753,27 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
}
- } else {
+ break;
+
+ case TCG_COND_TSTNE:
+ case TCG_COND_TSTEQ:
+ if (const_args[2]) {
+ /* (x & 0) == 0 */
+ tcg_out_dupi_vec(s, type, MO_8, a0,
+ -(cond == TCG_COND_TSTEQ));
+ break;
+ }
+ if (is_scalar) {
+ tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a2);
+ }
+ if (cond == TCG_COND_TSTEQ) {
+ tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
+ }
+ break;
+
+ default:
if (const_args[2]) {
if (is_scalar) {
insn = cmp0_scalar_insn[cond];
@@ -2791,6 +2812,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
}
+ break;
}
}
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PULL 4/5] tcg/arm: Support TCG_TARGET_HAS_tst_vec
2024-05-23 16:15 [PULL 0/5] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2024-05-23 16:15 ` [PULL 3/5] tcg/aarch64: Support TCG_TARGET_HAS_tst_vec Richard Henderson
@ 2024-05-23 16:15 ` Richard Henderson
2024-05-23 16:15 ` [PULL 5/5] accel/tcg: Init tb size and icount before plugin_gen_tb_end Richard Henderson
2024-05-24 5:06 ` [PULL 0/5] tcg patch queue Richard Henderson
5 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2024-05-23 16:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 23 ++++++++++++++++++++---
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 434a892e07..fb7261499b 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -150,7 +150,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
-#define TCG_TARGET_HAS_tst_vec 0
+#define TCG_TARGET_HAS_tst_vec 1
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 6a04c73c76..3de5f50b62 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2740,17 +2740,33 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_cmp_vec:
{
TCGCond cond = args[3];
+ ARMInsn insn;
- if (cond == TCG_COND_NE) {
+ switch (cond) {
+ case TCG_COND_NE:
if (const_args[2]) {
tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
} else {
tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
}
- } else {
- ARMInsn insn;
+ break;
+ case TCG_COND_TSTNE:
+ case TCG_COND_TSTEQ:
+ if (const_args[2]) {
+ /* (x & 0) == 0 */
+ tcg_out_dupi_vec(s, type, MO_8, a0,
+ -(cond == TCG_COND_TSTEQ));
+ break;
+ }
+ tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2);
+ if (cond == TCG_COND_TSTEQ) {
+ tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
+ }
+ break;
+
+ default:
if (const_args[2]) {
insn = vec_cmp0_insn[cond];
if (insn) {
@@ -2769,6 +2785,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_debug_assert(insn != 0);
}
tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
+ break;
}
}
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PULL 5/5] accel/tcg: Init tb size and icount before plugin_gen_tb_end
2024-05-23 16:15 [PULL 0/5] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2024-05-23 16:15 ` [PULL 4/5] tcg/arm: " Richard Henderson
@ 2024-05-23 16:15 ` Richard Henderson
2024-05-24 5:06 ` [PULL 0/5] tcg patch queue Richard Henderson
5 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2024-05-23 16:15 UTC (permalink / raw)
To: qemu-devel; +Cc: Bernhard Beschow, Pierrick Bouvier
When passing disassembly data to plugin callbacks,
translator_st_len relies on db->tb->size having been set.
Fixes: 4c833c60e047 ("disas: Use translator_st to get disassembly data")
Reported-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
accel/tcg/translator.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index c56967eecd..113edcffe3 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -214,14 +214,14 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
set_can_do_io(db, true);
tcg_ctx->emit_before_op = NULL;
+ /* May be used by disas_log or plugin callbacks. */
+ tb->size = db->pc_next - db->pc_first;
+ tb->icount = db->num_insns;
+
if (plugin_enabled) {
plugin_gen_tb_end(cpu, db->num_insns);
}
- /* The disas_log hook may use these values rather than recompute. */
- tb->size = db->pc_next - db->pc_first;
- tb->icount = db->num_insns;
-
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
&& qemu_log_in_addr_range(db->pc_first)) {
FILE *logfile = qemu_log_trylock();
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PULL 0/5] tcg patch queue
2024-05-23 16:15 [PULL 0/5] tcg patch queue Richard Henderson
` (4 preceding siblings ...)
2024-05-23 16:15 ` [PULL 5/5] accel/tcg: Init tb size and icount before plugin_gen_tb_end Richard Henderson
@ 2024-05-24 5:06 ` Richard Henderson
5 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2024-05-24 5:06 UTC (permalink / raw)
To: qemu-devel
On 5/23/24 09:15, Richard Henderson wrote:
> The following changes since commit 7e1c0047015ffbd408e1aa4a5ec1abe4751dbf7e:
>
> Merge tag 'migration-20240522-pull-request' ofhttps://gitlab.com/farosas/qemu into staging (2024-05-22 15:32:25 -0700)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240523
>
> for you to fetch changes up to bfd43cccab9fb77b8405ca556fc2f2ed3b2920a3:
>
> accel/tcg: Init tb size and icount before plugin_gen_tb_end (2024-05-22 19:05:26 -0700)
>
> ----------------------------------------------------------------
> tcg: Introduce TCG_TARGET_HAS_tst_vec
> accel/tcg: Init tb size and icount before plugin_gen_tb_end
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 7+ messages in thread