From: nifan.cxl@gmail.com
To: qemu-devel@nongnu.org
Cc: jonathan.cameron@huawei.com, linux-cxl@vger.kernel.org,
gregory.price@memverge.com, ira.weiny@intel.com,
dan.j.williams@intel.com, a.manzanares@samsung.com,
dave@stgolabs.net, nmtadam.samsung@gmail.com,
nifan.cxl@gmail.com, jim.harris@samsung.com,
Jorgen.Hansen@wdc.com, wj28.lee@gmail.com, armbru@redhat.com,
mst@redhat.com, Fan Ni <fan.ni@samsung.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: [PATCH v8 07/14] hw/mem/cxl-type3: Refactor ct3_build_cdat_entries_for_mr to take mr size instead of mr as argument
Date: Thu, 23 May 2024 10:44:47 -0700 [thread overview]
Message-ID: <20240523174651.1089554-8-nifan.cxl@gmail.com> (raw)
In-Reply-To: <20240523174651.1089554-1-nifan.cxl@gmail.com>
From: Fan Ni <fan.ni@samsung.com>
The function ct3_build_cdat_entries_for_mr only uses size of the passed
memory region argument, refactor the function definition to make the passed
arguments more specific.
Reviewed-by: Gregory Price <gregory.price@memverge.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Fan Ni <fan.ni@samsung.com>
---
hw/mem/cxl_type3.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 06c6f9bb78..51be50ce87 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -44,7 +44,7 @@ enum {
};
static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
- int dsmad_handle, MemoryRegion *mr,
+ int dsmad_handle, uint64_t size,
bool is_pmem, uint64_t dpa_base)
{
CDATDsmas *dsmas;
@@ -63,7 +63,7 @@ static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
.DSMADhandle = dsmad_handle,
.flags = is_pmem ? CDAT_DSMAS_FLAG_NV : 0,
.DPA_base = dpa_base,
- .DPA_length = memory_region_size(mr),
+ .DPA_length = size,
};
/* For now, no memory side cache, plausiblish numbers */
@@ -132,7 +132,7 @@ static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
*/
.EFI_memory_type_attr = is_pmem ? 2 : 1,
.DPA_offset = 0,
- .DPA_length = memory_region_size(mr),
+ .DPA_length = size,
};
/* Header always at start of structure */
@@ -149,6 +149,7 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
g_autofree CDATSubHeader **table = NULL;
CXLType3Dev *ct3d = priv;
MemoryRegion *volatile_mr = NULL, *nonvolatile_mr = NULL;
+ uint64_t vmr_size = 0, pmr_size = 0;
int dsmad_handle = 0;
int cur_ent = 0;
int len = 0;
@@ -163,6 +164,7 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
return -EINVAL;
}
len += CT3_CDAT_NUM_ENTRIES;
+ vmr_size = memory_region_size(volatile_mr);
}
if (ct3d->hostpmem) {
@@ -171,21 +173,22 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
return -EINVAL;
}
len += CT3_CDAT_NUM_ENTRIES;
+ pmr_size = memory_region_size(nonvolatile_mr);
}
table = g_malloc0(len * sizeof(*table));
/* Now fill them in */
if (volatile_mr) {
- ct3_build_cdat_entries_for_mr(table, dsmad_handle++, volatile_mr,
+ ct3_build_cdat_entries_for_mr(table, dsmad_handle++, vmr_size,
false, 0);
cur_ent = CT3_CDAT_NUM_ENTRIES;
}
if (nonvolatile_mr) {
- uint64_t base = volatile_mr ? memory_region_size(volatile_mr) : 0;
+ uint64_t base = vmr_size;
ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_handle++,
- nonvolatile_mr, true, base);
+ pmr_size, true, base);
cur_ent += CT3_CDAT_NUM_ENTRIES;
}
assert(len == cur_ent);
--
2.43.0
next prev parent reply other threads:[~2024-05-23 17:50 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-23 17:44 [PATCH v8 00/14] Enabling DCD emulation support in Qemu nifan.cxl
2024-05-23 17:44 ` [PATCH v8 01/14] hw/cxl/mailbox: change CCI cmd set structure to be a member, not a reference nifan.cxl
2024-05-23 17:44 ` [PATCH v8 02/14] hw/cxl/mailbox: interface to add CCI commands to an existing CCI nifan.cxl
2024-05-23 17:44 ` [PATCH v8 03/14] hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output payload of identify memory device command nifan.cxl
2024-05-23 17:44 ` [PATCH v8 04/14] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support nifan.cxl
2024-05-23 17:44 ` [PATCH v8 05/14] include/hw/cxl/cxl_device: Rename mem_size as static_mem_size for type3 memory devices nifan.cxl
2024-05-23 17:44 ` [PATCH v8 06/14] hw/mem/cxl_type3: Add support to create DC regions to " nifan.cxl
2024-05-27 7:42 ` Zhijian Li (Fujitsu) via
2024-05-23 17:44 ` nifan.cxl [this message]
2024-05-23 17:44 ` [PATCH v8 08/14] hw/mem/cxl_type3: Add host backend and address space handling for DC regions nifan.cxl
2024-06-03 12:27 ` Jonathan Cameron via
2024-06-03 15:04 ` Michael S. Tsirkin
2024-06-03 17:27 ` Jonathan Cameron via
2024-05-23 17:44 ` [PATCH v8 09/14] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support nifan.cxl
2024-05-23 17:44 ` [PATCH v8 10/14] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response nifan.cxl
2024-05-23 17:44 ` [PATCH v8 11/14] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents nifan.cxl
2024-06-04 7:12 ` Markus Armbruster
2024-06-04 11:55 ` Jonathan Cameron via
2024-06-04 14:49 ` Markus Armbruster
2025-09-02 10:39 ` Alireza Sanaee via
2025-09-02 15:59 ` Ira Weiny
2025-09-04 8:44 ` Alireza Sanaee via
2024-05-23 17:44 ` [PATCH v8 12/14] hw/mem/cxl_type3: Add DPA range validation for accesses to DC regions nifan.cxl
2024-05-23 17:44 ` [PATCH v8 13/14] hw/cxl/cxl-mailbox-utils: Add superset extent release mailbox support nifan.cxl
2024-05-23 17:44 ` [PATCH v8 14/14] hw/mem/cxl_type3: Allow to release extent superset in QMP interface nifan.cxl
2024-06-03 13:51 ` [PATCH v8 00/14] Enabling DCD emulation support in Qemu Jonathan Cameron via
2025-06-25 14:22 ` Alireza Sanaee via
2025-06-26 16:39 ` Fan Ni
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