From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-ppc@nongnu.org, Chinmay Rath <rathc@linux.ibm.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 19/72] target/ppc: Move VMX storage access instructions to decodetree
Date: Fri, 24 May 2024 09:06:52 +1000 [thread overview]
Message-ID: <20240523230747.45703-20-npiggin@gmail.com> (raw)
In-Reply-To: <20240523230747.45703-1-npiggin@gmail.com>
From: Chinmay Rath <rathc@linux.ibm.com>
Moving the following instructions to decodetree specification :
{l,st}ve{b,h,w}x,
{l,st}v{x,xl},
lvs{l,r} : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/helper.h | 12 +-
target/ppc/insn32.decode | 17 +++
target/ppc/mem_helper.c | 12 +-
target/ppc/translate.c | 2 -
target/ppc/translate/vmx-impl.c.inc | 221 ++++++++++++----------------
target/ppc/translate/vmx-ops.c.inc | 19 ---
6 files changed, 120 insertions(+), 163 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4267917615..6d6f31366c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -267,12 +267,12 @@ DEF_HELPER_5(VMSUMSHS, void, env, avr, avr, avr, avr)
DEF_HELPER_FLAGS_5(VMLADDUHM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env)
-DEF_HELPER_3(lvebx, void, env, avr, tl)
-DEF_HELPER_3(lvehx, void, env, avr, tl)
-DEF_HELPER_3(lvewx, void, env, avr, tl)
-DEF_HELPER_3(stvebx, void, env, avr, tl)
-DEF_HELPER_3(stvehx, void, env, avr, tl)
-DEF_HELPER_3(stvewx, void, env, avr, tl)
+DEF_HELPER_3(LVEBX, void, env, avr, tl)
+DEF_HELPER_3(LVEHX, void, env, avr, tl)
+DEF_HELPER_3(LVEWX, void, env, avr, tl)
+DEF_HELPER_3(STVEBX, void, env, avr, tl)
+DEF_HELPER_3(STVEHX, void, env, avr, tl)
+DEF_HELPER_3(STVEWX, void, env, avr, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_4(lxvl, void, env, tl, vsr, tl)
DEF_HELPER_4(lxvll, void, env, tl, vsr, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index dc62bc90aa..11be21d230 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -661,6 +661,23 @@ DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
VPMSUMD 000100 ..... ..... ..... 10011001000 @VX
+## Vector Load/Store Instructions
+
+LVEBX 011111 ..... ..... ..... 0000000111 - @X
+LVEHX 011111 ..... ..... ..... 0000100111 - @X
+LVEWX 011111 ..... ..... ..... 0001000111 - @X
+LVX 011111 ..... ..... ..... 0001100111 - @X
+LVXL 011111 ..... ..... ..... 0101100111 - @X
+
+STVEBX 011111 ..... ..... ..... 0010000111 - @X
+STVEHX 011111 ..... ..... ..... 0010100111 - @X
+STVEWX 011111 ..... ..... ..... 0011000111 - @X
+STVX 011111 ..... ..... ..... 0011100111 - @X
+STVXL 011111 ..... ..... ..... 0111100111 - @X
+
+LVSL 011111 ..... ..... ..... 0000000110 - @X
+LVSR 011111 ..... ..... ..... 0000100110 - @X
+
## Vector Integer Instructions
VCMPEQUB 000100 ..... ..... ..... . 0000000110 @VC
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index ea7e8443a8..f88155ad45 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -404,9 +404,9 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
} \
}
#define I(x) (x)
-LVE(lvebx, cpu_ldub_data_ra, I, u8)
-LVE(lvehx, cpu_lduw_data_ra, bswap16, u16)
-LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
+LVE(LVEBX, cpu_ldub_data_ra, I, u8)
+LVE(LVEHX, cpu_lduw_data_ra, bswap16, u16)
+LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32)
#undef I
#undef LVE
@@ -432,9 +432,9 @@ LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
} \
}
#define I(x) (x)
-STVE(stvebx, cpu_stb_data_ra, I, u8)
-STVE(stvehx, cpu_stw_data_ra, bswap16, u16)
-STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
+STVE(STVEBX, cpu_stb_data_ra, I, u8)
+STVE(STVEHX, cpu_stw_data_ra, bswap16, u16)
+STVE(STVEWX, cpu_stl_data_ra, bswap32, u32)
#undef I
#undef LVE
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2cfa7d37ee..2c39605273 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5790,8 +5790,6 @@ GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
PPC_BOOKE, PPC2_BOOKE206),
GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
PPC_440_SPEC),
-GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
-GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index b56e615c24..4d5e743cfe 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -14,125 +14,88 @@ static inline TCGv_ptr gen_avr_ptr(int reg)
return r;
}
-#define GEN_VR_LDX(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 avr; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- avr = tcg_temp_new_i64(); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- tcg_gen_andi_tl(EA, EA, ~0xf); \
- /* \
- * We only need to swap high and low halves. gen_qemu_ld64_i64 \
- * does necessary 64-bit byteswap already. \
- */ \
- if (ctx->le_mode) { \
- gen_qemu_ld64_i64(ctx, avr, EA); \
- set_avr64(rD(ctx->opcode), avr, false); \
- tcg_gen_addi_tl(EA, EA, 8); \
- gen_qemu_ld64_i64(ctx, avr, EA); \
- set_avr64(rD(ctx->opcode), avr, true); \
- } else { \
- gen_qemu_ld64_i64(ctx, avr, EA); \
- set_avr64(rD(ctx->opcode), avr, true); \
- tcg_gen_addi_tl(EA, EA, 8); \
- gen_qemu_ld64_i64(ctx, avr, EA); \
- set_avr64(rD(ctx->opcode), avr, false); \
- } \
-}
-
-#define GEN_VR_STX(name, opc2, opc3) \
-static void gen_st##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 avr; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- avr = tcg_temp_new_i64(); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- tcg_gen_andi_tl(EA, EA, ~0xf); \
- /* \
- * We only need to swap high and low halves. gen_qemu_st64_i64 \
- * does necessary 64-bit byteswap already. \
- */ \
- if (ctx->le_mode) { \
- get_avr64(avr, rD(ctx->opcode), false); \
- gen_qemu_st64_i64(ctx, avr, EA); \
- tcg_gen_addi_tl(EA, EA, 8); \
- get_avr64(avr, rD(ctx->opcode), true); \
- gen_qemu_st64_i64(ctx, avr, EA); \
- } else { \
- get_avr64(avr, rD(ctx->opcode), true); \
- gen_qemu_st64_i64(ctx, avr, EA); \
- tcg_gen_addi_tl(EA, EA, 8); \
- get_avr64(avr, rD(ctx->opcode), false); \
- gen_qemu_st64_i64(ctx, avr, EA); \
- } \
-}
-
-#define GEN_VR_LVE(name, opc2, opc3, size) \
-static void gen_lve##name(DisasContext *ctx) \
- { \
- TCGv EA; \
- TCGv_ptr rs; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- if (size > 1) { \
- tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
- } \
- rs = gen_avr_ptr(rS(ctx->opcode)); \
- gen_helper_lve##name(tcg_env, rs, EA); \
- }
-
-#define GEN_VR_STVE(name, opc2, opc3, size) \
-static void gen_stve##name(DisasContext *ctx) \
- { \
- TCGv EA; \
- TCGv_ptr rs; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- if (size > 1) { \
- tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
- } \
- rs = gen_avr_ptr(rS(ctx->opcode)); \
- gen_helper_stve##name(tcg_env, rs, EA); \
- }
+static bool trans_LVX(DisasContext *ctx, arg_X *a)
+{
+ TCGv EA;
+ TCGv_i64 avr;
+ REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
+ REQUIRE_VECTOR(ctx);
+ gen_set_access_type(ctx, ACCESS_INT);
+ avr = tcg_temp_new_i64();
+ EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
+ tcg_gen_andi_tl(EA, EA, ~0xf);
+ /*
+ * We only need to swap high and low halves. gen_qemu_ld64_i64
+ * does necessary 64-bit byteswap already.
+ */
+ gen_qemu_ld64_i64(ctx, avr, EA);
+ set_avr64(a->rt, avr, !ctx->le_mode);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64_i64(ctx, avr, EA);
+ set_avr64(a->rt, avr, ctx->le_mode);
+ return true;
+}
-GEN_VR_LDX(lvx, 0x07, 0x03);
/* As we don't emulate the cache, lvxl is strictly equivalent to lvx */
-GEN_VR_LDX(lvxl, 0x07, 0x0B);
+QEMU_FLATTEN
+static bool trans_LVXL(DisasContext *ctx, arg_LVXL *a)
+{
+ return trans_LVX(ctx, a);
+}
-GEN_VR_LVE(bx, 0x07, 0x00, 1);
-GEN_VR_LVE(hx, 0x07, 0x01, 2);
-GEN_VR_LVE(wx, 0x07, 0x02, 4);
+static bool trans_STVX(DisasContext *ctx, arg_STVX *a)
+{
+ TCGv EA;
+ TCGv_i64 avr;
+ REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
+ REQUIRE_VECTOR(ctx);
+ gen_set_access_type(ctx, ACCESS_INT);
+ avr = tcg_temp_new_i64();
+ EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
+ tcg_gen_andi_tl(EA, EA, ~0xf);
+ /*
+ * We only need to swap high and low halves. gen_qemu_st64_i64
+ * does necessary 64-bit byteswap already.
+ */
+ get_avr64(avr, a->rt, !ctx->le_mode);
+ gen_qemu_st64_i64(ctx, avr, EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ get_avr64(avr, a->rt, ctx->le_mode);
+ gen_qemu_st64_i64(ctx, avr, EA);
+ return true;
+}
-GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is strictly equivalent to stvx */
-GEN_VR_STX(svxl, 0x07, 0x0F);
+QEMU_FLATTEN
+static bool trans_STVXL(DisasContext *ctx, arg_STVXL *a)
+{
+ return trans_STVX(ctx, a);
+}
+
+static bool do_ldst_ve_X(DisasContext *ctx, arg_X *a, int size,
+ void (*helper)(TCGv_env, TCGv_ptr, TCGv))
+{
+ TCGv EA;
+ TCGv_ptr vrt;
+ REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
+ REQUIRE_VECTOR(ctx);
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
+ if (size > 1) {
+ tcg_gen_andi_tl(EA, EA, ~(size - 1));
+ }
+ vrt = gen_avr_ptr(a->rt);
+ helper(tcg_env, vrt, EA);
+ return true;
+}
+
+TRANS(LVEBX, do_ldst_ve_X, 1, gen_helper_LVEBX);
+TRANS(LVEHX, do_ldst_ve_X, 2, gen_helper_LVEHX);
+TRANS(LVEWX, do_ldst_ve_X, 4, gen_helper_LVEWX);
-GEN_VR_STVE(bx, 0x07, 0x04, 1);
-GEN_VR_STVE(hx, 0x07, 0x05, 2);
-GEN_VR_STVE(wx, 0x07, 0x06, 4);
+TRANS(STVEBX, do_ldst_ve_X, 1, gen_helper_STVEBX);
+TRANS(STVEHX, do_ldst_ve_X, 2, gen_helper_STVEHX);
+TRANS(STVEWX, do_ldst_ve_X, 4, gen_helper_STVEWX);
static void gen_mfvscr(DisasContext *ctx)
{
@@ -460,15 +423,17 @@ static void trans_vmrgow(DisasContext *ctx)
* Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
* Bytes sh:sh+15 of X are placed into vD.
*/
-static void trans_lvsl(DisasContext *ctx)
+static bool trans_LVSL(DisasContext *ctx, arg_LVSL *a)
{
- int VT = rD(ctx->opcode);
TCGv_i64 result = tcg_temp_new_i64();
TCGv_i64 sh = tcg_temp_new_i64();
TCGv EA = tcg_temp_new();
+ REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
+ REQUIRE_VECTOR(ctx);
+
/* Get sh(from description) by anding EA with 0xf. */
- gen_addr_reg_index(ctx, EA);
+ EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
tcg_gen_extu_tl_i64(sh, EA);
tcg_gen_andi_i64(sh, sh, 0xfULL);
@@ -478,13 +443,14 @@ static void trans_lvsl(DisasContext *ctx)
*/
tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
- set_avr64(VT, result, true);
+ set_avr64(a->rt, result, true);
/*
* Create bytes sh+8:sh+15 of X(from description) and place them in
* lower doubleword of vD.
*/
tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
- set_avr64(VT, result, false);
+ set_avr64(a->rt, result, false);
+ return true;
}
/*
@@ -494,16 +460,17 @@ static void trans_lvsl(DisasContext *ctx)
* Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
* Bytes (16-sh):(31-sh) of X are placed into vD.
*/
-static void trans_lvsr(DisasContext *ctx)
+static bool trans_LVSR(DisasContext *ctx, arg_LVSR *a)
{
- int VT = rD(ctx->opcode);
TCGv_i64 result = tcg_temp_new_i64();
TCGv_i64 sh = tcg_temp_new_i64();
TCGv EA = tcg_temp_new();
+ REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
+ REQUIRE_VECTOR(ctx);
/* Get sh(from description) by anding EA with 0xf. */
- gen_addr_reg_index(ctx, EA);
+ EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
tcg_gen_extu_tl_i64(sh, EA);
tcg_gen_andi_i64(sh, sh, 0xfULL);
@@ -513,13 +480,14 @@ static void trans_lvsr(DisasContext *ctx)
*/
tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
- set_avr64(VT, result, true);
+ set_avr64(a->rt, result, true);
/*
* Create bytes (24-sh):(32-sh) of X(from description) and place them in
* lower doubleword of vD.
*/
tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
- set_avr64(VT, result, false);
+ set_avr64(a->rt, result, false);
+ return true;
}
/*
@@ -1158,8 +1126,6 @@ GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
GEN_VXFORM_HETRO(vextubrx, 6, 28)
GEN_VXFORM_HETRO(vextuhrx, 6, 29)
GEN_VXFORM_HETRO(vextuwrx, 6, 30)
-GEN_VXFORM_TRANS(lvsl, 6, 31)
-GEN_VXFORM_TRANS(lvsr, 6, 32)
GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
vextuwrx, PPC_NONE, PPC2_ISA300)
@@ -3365,11 +3331,6 @@ TRANS_FLAGS2(ISA310, VMODUQ, do_vx_helper, gen_helper_VMODUQ)
#undef DIVS64
#undef DIVU64
-#undef GEN_VR_LDX
-#undef GEN_VR_STX
-#undef GEN_VR_LVE
-#undef GEN_VR_STVE
-
#undef GEN_VX_LOGICAL
#undef GEN_VX_LOGICAL_207
#undef GEN_VXFORM
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 33fec8aca4..672fba3796 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -1,22 +1,3 @@
-#define GEN_VR_LDX(name, opc2, opc3) \
-GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
-#define GEN_VR_STX(name, opc2, opc3) \
-GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
-#define GEN_VR_LVE(name, opc2, opc3) \
- GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
-#define GEN_VR_STVE(name, opc2, opc3) \
- GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
-GEN_VR_LDX(lvx, 0x07, 0x03),
-GEN_VR_LDX(lvxl, 0x07, 0x0B),
-GEN_VR_LVE(bx, 0x07, 0x00),
-GEN_VR_LVE(hx, 0x07, 0x01),
-GEN_VR_LVE(wx, 0x07, 0x02),
-GEN_VR_STX(svx, 0x07, 0x07),
-GEN_VR_STX(svxl, 0x07, 0x0F),
-GEN_VR_STVE(bx, 0x07, 0x04),
-GEN_VR_STVE(hx, 0x07, 0x05),
-GEN_VR_STVE(wx, 0x07, 0x06),
-
#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
--
2.43.0
next prev parent reply other threads:[~2024-05-23 23:10 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-23 23:06 [PULL 00/72] ppc-for-9.1-1 queue Nicholas Piggin
2024-05-23 23:06 ` [PULL 01/72] spapr: avoid overhead of finding vhyp class in critical operations Nicholas Piggin
2024-05-23 23:06 ` [PULL 02/72] ppc/spapr: Add ibm,pi-features Nicholas Piggin
2024-05-23 23:06 ` [PULL 03/72] target/ppc: Fix broadcast tlbie synchronisation Nicholas Piggin
2024-05-23 23:06 ` [PULL 04/72] tcg/cputlb: Remove non-synced variants of global TLB flushes Nicholas Piggin
2024-05-23 23:06 ` [PULL 05/72] tcg/cputlb: remove other-cpu capability from TLB flushing Nicholas Piggin
2024-05-23 23:06 ` [PULL 06/72] target/ppc: Move sync instructions to decodetree Nicholas Piggin
2024-05-23 23:06 ` [PULL 07/72] target/ppc: Fix embedded memory barriers Nicholas Piggin
2024-05-23 23:06 ` [PULL 08/72] target/ppc: Add ISA v3.1 variants of sync instruction Nicholas Piggin
2024-05-23 23:06 ` [PULL 09/72] target/ppc: Merge various fpu helpers Nicholas Piggin
2024-05-23 23:06 ` [PULL 10/72] target/ppc: Move floating-point arithmetic instructions to decodetree Nicholas Piggin
2024-05-23 23:06 ` [PULL 11/72] target/ppc: Move mul{li, lw, lwo, hw, hwu} " Nicholas Piggin
2024-05-23 23:06 ` [PULL 12/72] target/ppc: Make divw[u] handler method decodetree compatible Nicholas Piggin
2024-05-23 23:06 ` [PULL 13/72] target/ppc: Move divw[u, e, eu] instructions to decodetree Nicholas Piggin
2024-05-23 23:06 ` [PULL 14/72] target/ppc: Move neg, darn, mod{sw, uw} " Nicholas Piggin
2024-05-23 23:06 ` [PULL 15/72] target/ppc: Move multiply fixed-point insns (64-bit operands) " Nicholas Piggin
2024-05-23 23:06 ` [PULL 16/72] target/ppc: Move div/mod fixed-point insns (64 bits " Nicholas Piggin
2024-05-23 23:06 ` [PULL 17/72] target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions " Nicholas Piggin
2024-05-23 23:06 ` [PULL 18/72] target/ppc: Move logical fixed-point " Nicholas Piggin
2024-05-23 23:06 ` Nicholas Piggin [this message]
2024-05-23 23:06 ` [PULL 20/72] target/ppc: Move VMX integer logical " Nicholas Piggin
2024-05-23 23:06 ` [PULL 21/72] target/ppc: Move VMX integer max/min " Nicholas Piggin
2024-05-23 23:06 ` [PULL 22/72] This commit is preparatory to the addition of Branch History Rolling Buffer (BHRB) functionality, which is being provided today starting with the P8 processor Nicholas Piggin
2024-05-23 23:06 ` [PULL 23/72] This commit continues adding support for the Branch History Rolling Buffer (BHRB) as is provided starting with the P8 processor and continuing with its successors. This commit is limited to the recording and filtering of taken branches Nicholas Piggin
2024-05-23 23:06 ` [PULL 24/72] Add support for the clrbhrb and mfbhrbe instructions Nicholas Piggin
2024-05-23 23:06 ` [PULL 25/72] Adds migration support for Branch History Rolling Buffer (BHRB) internal state Nicholas Piggin
2024-05-31 20:06 ` Fabiano Rosas
2024-06-03 4:32 ` Nicholas Piggin
2024-05-23 23:06 ` [PULL 26/72] target/ppc: larx/stcx generation need only apply DEF_MEMOP() once Nicholas Piggin
2024-05-23 23:07 ` [PULL 27/72] target/ppc: Remove redundant MEMOP_GET_SIZE macro Nicholas Piggin
2024-05-23 23:07 ` [PULL 28/72] target/ppc: Make checkstop actually stop the system Nicholas Piggin
2024-05-23 23:07 ` [PULL 29/72] target/ppc: improve checkstop logging Nicholas Piggin
2024-05-23 23:07 ` [PULL 30/72] target/ppc: Implement attn instruction on BookS 64-bit processors Nicholas Piggin
2024-05-23 23:07 ` [PULL 31/72] target/ppc: BookE DECAR SPR is 32-bit Nicholas Piggin
2024-05-23 23:07 ` [PULL 32/72] target/ppc: Add PPR32 SPR Nicholas Piggin
2024-05-23 23:07 ` [PULL 33/72] target/ppc: add helper to write per-LPAR SPRs Nicholas Piggin
2024-05-23 23:07 ` [PULL 34/72] target/ppc: Add SMT support to simple SPRs Nicholas Piggin
2024-05-23 23:07 ` [PULL 35/72] target/ppc: Add SMT support to PTCR SPR Nicholas Piggin
2024-05-23 23:07 ` [PULL 36/72] target/ppc: Implement LDBAR, TTR SPRs Nicholas Piggin
2024-05-23 23:07 ` [PULL 37/72] target/ppc: Implement SPRC/SPRD SPRs Nicholas Piggin
2024-05-23 23:07 ` [PULL 38/72] target/ppc: add SMT support to msgsnd broadcast Nicholas Piggin
2024-05-23 23:07 ` [PULL 39/72] target/ppc: Remove unused struct 'mmu_ctx_hash32' Nicholas Piggin
2024-05-23 23:07 ` [PULL 40/72] target/ppc: Remove unused helper Nicholas Piggin
2024-05-23 23:07 ` [PULL 41/72] target/ppc/mmu_common.c: Move calculation of a value closer to its usage Nicholas Piggin
2024-05-23 23:07 ` [PULL 42/72] target/ppc/mmu_common.c: Remove unneeded local variable Nicholas Piggin
2024-05-23 23:07 ` [PULL 43/72] target/ppc/mmu_common.c: Simplify checking for real mode Nicholas Piggin
2024-05-23 23:07 ` [PULL 44/72] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU Nicholas Piggin
2024-05-23 23:07 ` [PULL 45/72] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 46/72] target/ppc/mmu_common.c: Move else branch to avoid large if block Nicholas Piggin
2024-05-23 23:07 ` [PULL 47/72] target/ppc/mmu_common.c: Move some debug logging Nicholas Piggin
2024-05-23 23:07 ` [PULL 48/72] target/ppc/mmu_common.c: Eliminate ret from mmu6xx_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 49/72] target/ppc/mmu_common.c: Split out BookE cases before checking real mode Nicholas Piggin
2024-05-23 23:07 ` [PULL 50/72] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() Nicholas Piggin
2024-05-23 23:07 ` [PULL 51/72] target/ppc/mmu_common.c: Inline and remove check_physical() Nicholas Piggin
2024-05-23 23:07 ` [PULL 52/72] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls Nicholas Piggin
2024-05-23 23:07 ` [PULL 53/72] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 54/72] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 55/72] target/ppc/mmu_common.c: Don't use mmu_ctx_t for mmu40x_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 56/72] target/ppc/mmu_common.c: Don't use mmu_ctx_t in mmubooke_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 57/72] target/ppc/mmu_common.c: Don't use mmu_ctx_t in mmubooke206_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 58/72] target/ppc/mmu_common.c: Remove BookE from direct store handling Nicholas Piggin
2024-05-23 23:07 ` [PULL 59/72] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 60/72] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 1 Nicholas Piggin
2024-05-23 23:07 ` [PULL 61/72] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 2 Nicholas Piggin
2024-05-23 23:07 ` [PULL 62/72] target/ppc/mmu_common.c: Split off real mode handling from get_physical_address_wtlb() Nicholas Piggin
2024-05-23 23:07 ` [PULL 63/72] target/ppc/mmu_common.c: Split off 40x cases from ppc_jumbo_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 64/72] target/ppc/mmu_common.c: Transform ppc_jumbo_xlate() into ppc_6xx_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 65/72] target/ppc/mmu_common.c: Move mmu_ctx_t type to mmu_common.c Nicholas Piggin
2024-05-23 23:07 ` [PULL 66/72] target/ppc: Remove id_tlbs flag from CPU env Nicholas Piggin
2024-05-23 23:07 ` [PULL 67/72] target/ppc: Split off common embedded TLB init Nicholas Piggin
2024-05-23 23:07 ` [PULL 68/72] target/ppc/mmu-hash32.c: Drop a local variable Nicholas Piggin
2024-05-23 23:07 ` [PULL 69/72] target/ppc/mmu-radix64.c: " Nicholas Piggin
2024-05-23 23:07 ` [PULL 70/72] target/ppc: Add a function to check for page protection bit Nicholas Piggin
2024-05-23 23:07 ` [PULL 71/72] target/ppc: Move out BookE and related MMU functions from mmu_common.c Nicholas Piggin
2024-05-23 23:07 ` [PULL 72/72] target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() Nicholas Piggin
2024-05-23 23:31 ` [PULL 00/72] ppc-for-9.1-1 queue Nicholas Piggin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240523230747.45703-20-npiggin@gmail.com \
--to=npiggin@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=rathc@linux.ibm.com \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).