From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
qemu-ppc@nongnu.org, "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 03/72] target/ppc: Fix broadcast tlbie synchronisation
Date: Fri, 24 May 2024 09:06:36 +1000 [thread overview]
Message-ID: <20240523230747.45703-4-npiggin@gmail.com> (raw)
In-Reply-To: <20240523230747.45703-1-npiggin@gmail.com>
With mttcg, broadcast tlbie instructions do not wait until other vCPUs
have been kicked out of TCG execution before they complete (including
necessary subsequent tlbsync, etc., instructions). This is contrary to
the ISA, and it permits other vCPUs to use translations after the TLB
flush. For example:
CPU0
// *memP is initially 0, memV maps to memP with *pte
*pte = 0;
ptesync ; tlbie ; eieio ; tlbsync ; ptesync
*memP = 1;
CPU1
assert(*memV == 0);
It is possible for the assertion to fail because CPU1 translates memV
using the TLB after CPU0 has stored 1 to the underlying memory. This
race was observed with a careful test case where CPU1 checks run in a
very large expensive TB so it can run for the entire CPU0 period between
clearing the pte and storing the memory, but host vCPU thread preemption
could cause the race to hit anywhere.
As explained in commit 4ddc104689b ("target/ppc: Fix tlbie"), it is not
enough to just use tlb_flush_all_cpus_synced(), because that does not
execute until the calling CPU has finished its TB. It is also required
that the TB is ended at the point where the TLB flush must subsequently
take effect.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/helper_regs.c | 2 +-
target/ppc/mmu_helper.c | 2 +-
target/ppc/translate.c | 7 +++++++
target/ppc/translate/storage-ctrl-impl.c.inc | 7 +++++++
4 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 25258986e3..9094ae5004 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -334,7 +334,7 @@ void check_tlb_flush(CPUPPCState *env, bool global)
if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
- tlb_flush_all_cpus(cs);
+ tlb_flush_all_cpus_synced(cs);
return;
}
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index b35a93c198..d9d950e220 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -534,7 +534,7 @@ void helper_tlbie_isa300(CPUPPCState *env, target_ulong rb, target_ulong rs,
if (local) {
tlb_flush_page(env_cpu(env), addr);
} else {
- tlb_flush_page_all_cpus(env_cpu(env), addr);
+ tlb_flush_page_all_cpus_synced(env_cpu(env), addr);
}
return;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 49dee6cab0..24461c2d1b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3494,6 +3494,13 @@ static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
gen_helper_check_tlb_flush_local(tcg_env);
}
gen_set_label(l);
+ if (global) {
+ /*
+ * Global TLB flush uses async-work which must run before the
+ * next instruction, so this must be the last in the TB.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+ }
}
#else
static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index 74c23a4191..b8b4454663 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -224,6 +224,13 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
a->prs << TLBIE_F_PRS_SHIFT |
a->r << TLBIE_F_R_SHIFT |
local << TLBIE_F_LOCAL_SHIFT));
+ if (!local) {
+ /*
+ * Global TLB flush uses async-work which must run before the
+ * next instruction, so this must be the last in the TB.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+ }
return true;
#endif
--
2.43.0
next prev parent reply other threads:[~2024-05-23 23:10 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-23 23:06 [PULL 00/72] ppc-for-9.1-1 queue Nicholas Piggin
2024-05-23 23:06 ` [PULL 01/72] spapr: avoid overhead of finding vhyp class in critical operations Nicholas Piggin
2024-05-23 23:06 ` [PULL 02/72] ppc/spapr: Add ibm,pi-features Nicholas Piggin
2024-05-23 23:06 ` Nicholas Piggin [this message]
2024-05-23 23:06 ` [PULL 04/72] tcg/cputlb: Remove non-synced variants of global TLB flushes Nicholas Piggin
2024-05-23 23:06 ` [PULL 05/72] tcg/cputlb: remove other-cpu capability from TLB flushing Nicholas Piggin
2024-05-23 23:06 ` [PULL 06/72] target/ppc: Move sync instructions to decodetree Nicholas Piggin
2024-05-23 23:06 ` [PULL 07/72] target/ppc: Fix embedded memory barriers Nicholas Piggin
2024-05-23 23:06 ` [PULL 08/72] target/ppc: Add ISA v3.1 variants of sync instruction Nicholas Piggin
2024-05-23 23:06 ` [PULL 09/72] target/ppc: Merge various fpu helpers Nicholas Piggin
2024-05-23 23:06 ` [PULL 10/72] target/ppc: Move floating-point arithmetic instructions to decodetree Nicholas Piggin
2024-05-23 23:06 ` [PULL 11/72] target/ppc: Move mul{li, lw, lwo, hw, hwu} " Nicholas Piggin
2024-05-23 23:06 ` [PULL 12/72] target/ppc: Make divw[u] handler method decodetree compatible Nicholas Piggin
2024-05-23 23:06 ` [PULL 13/72] target/ppc: Move divw[u, e, eu] instructions to decodetree Nicholas Piggin
2024-05-23 23:06 ` [PULL 14/72] target/ppc: Move neg, darn, mod{sw, uw} " Nicholas Piggin
2024-05-23 23:06 ` [PULL 15/72] target/ppc: Move multiply fixed-point insns (64-bit operands) " Nicholas Piggin
2024-05-23 23:06 ` [PULL 16/72] target/ppc: Move div/mod fixed-point insns (64 bits " Nicholas Piggin
2024-05-23 23:06 ` [PULL 17/72] target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions " Nicholas Piggin
2024-05-23 23:06 ` [PULL 18/72] target/ppc: Move logical fixed-point " Nicholas Piggin
2024-05-23 23:06 ` [PULL 19/72] target/ppc: Move VMX storage access " Nicholas Piggin
2024-05-23 23:06 ` [PULL 20/72] target/ppc: Move VMX integer logical " Nicholas Piggin
2024-05-23 23:06 ` [PULL 21/72] target/ppc: Move VMX integer max/min " Nicholas Piggin
2024-05-23 23:06 ` [PULL 22/72] This commit is preparatory to the addition of Branch History Rolling Buffer (BHRB) functionality, which is being provided today starting with the P8 processor Nicholas Piggin
2024-05-23 23:06 ` [PULL 23/72] This commit continues adding support for the Branch History Rolling Buffer (BHRB) as is provided starting with the P8 processor and continuing with its successors. This commit is limited to the recording and filtering of taken branches Nicholas Piggin
2024-05-23 23:06 ` [PULL 24/72] Add support for the clrbhrb and mfbhrbe instructions Nicholas Piggin
2024-05-23 23:06 ` [PULL 25/72] Adds migration support for Branch History Rolling Buffer (BHRB) internal state Nicholas Piggin
2024-05-31 20:06 ` Fabiano Rosas
2024-06-03 4:32 ` Nicholas Piggin
2024-05-23 23:06 ` [PULL 26/72] target/ppc: larx/stcx generation need only apply DEF_MEMOP() once Nicholas Piggin
2024-05-23 23:07 ` [PULL 27/72] target/ppc: Remove redundant MEMOP_GET_SIZE macro Nicholas Piggin
2024-05-23 23:07 ` [PULL 28/72] target/ppc: Make checkstop actually stop the system Nicholas Piggin
2024-05-23 23:07 ` [PULL 29/72] target/ppc: improve checkstop logging Nicholas Piggin
2024-05-23 23:07 ` [PULL 30/72] target/ppc: Implement attn instruction on BookS 64-bit processors Nicholas Piggin
2024-05-23 23:07 ` [PULL 31/72] target/ppc: BookE DECAR SPR is 32-bit Nicholas Piggin
2024-05-23 23:07 ` [PULL 32/72] target/ppc: Add PPR32 SPR Nicholas Piggin
2024-05-23 23:07 ` [PULL 33/72] target/ppc: add helper to write per-LPAR SPRs Nicholas Piggin
2024-05-23 23:07 ` [PULL 34/72] target/ppc: Add SMT support to simple SPRs Nicholas Piggin
2024-05-23 23:07 ` [PULL 35/72] target/ppc: Add SMT support to PTCR SPR Nicholas Piggin
2024-05-23 23:07 ` [PULL 36/72] target/ppc: Implement LDBAR, TTR SPRs Nicholas Piggin
2024-05-23 23:07 ` [PULL 37/72] target/ppc: Implement SPRC/SPRD SPRs Nicholas Piggin
2024-05-23 23:07 ` [PULL 38/72] target/ppc: add SMT support to msgsnd broadcast Nicholas Piggin
2024-05-23 23:07 ` [PULL 39/72] target/ppc: Remove unused struct 'mmu_ctx_hash32' Nicholas Piggin
2024-05-23 23:07 ` [PULL 40/72] target/ppc: Remove unused helper Nicholas Piggin
2024-05-23 23:07 ` [PULL 41/72] target/ppc/mmu_common.c: Move calculation of a value closer to its usage Nicholas Piggin
2024-05-23 23:07 ` [PULL 42/72] target/ppc/mmu_common.c: Remove unneeded local variable Nicholas Piggin
2024-05-23 23:07 ` [PULL 43/72] target/ppc/mmu_common.c: Simplify checking for real mode Nicholas Piggin
2024-05-23 23:07 ` [PULL 44/72] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU Nicholas Piggin
2024-05-23 23:07 ` [PULL 45/72] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 46/72] target/ppc/mmu_common.c: Move else branch to avoid large if block Nicholas Piggin
2024-05-23 23:07 ` [PULL 47/72] target/ppc/mmu_common.c: Move some debug logging Nicholas Piggin
2024-05-23 23:07 ` [PULL 48/72] target/ppc/mmu_common.c: Eliminate ret from mmu6xx_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 49/72] target/ppc/mmu_common.c: Split out BookE cases before checking real mode Nicholas Piggin
2024-05-23 23:07 ` [PULL 50/72] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() Nicholas Piggin
2024-05-23 23:07 ` [PULL 51/72] target/ppc/mmu_common.c: Inline and remove check_physical() Nicholas Piggin
2024-05-23 23:07 ` [PULL 52/72] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls Nicholas Piggin
2024-05-23 23:07 ` [PULL 53/72] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 54/72] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 55/72] target/ppc/mmu_common.c: Don't use mmu_ctx_t for mmu40x_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 56/72] target/ppc/mmu_common.c: Don't use mmu_ctx_t in mmubooke_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 57/72] target/ppc/mmu_common.c: Don't use mmu_ctx_t in mmubooke206_get_physical_address() Nicholas Piggin
2024-05-23 23:07 ` [PULL 58/72] target/ppc/mmu_common.c: Remove BookE from direct store handling Nicholas Piggin
2024-05-23 23:07 ` [PULL 59/72] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 60/72] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 1 Nicholas Piggin
2024-05-23 23:07 ` [PULL 61/72] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 2 Nicholas Piggin
2024-05-23 23:07 ` [PULL 62/72] target/ppc/mmu_common.c: Split off real mode handling from get_physical_address_wtlb() Nicholas Piggin
2024-05-23 23:07 ` [PULL 63/72] target/ppc/mmu_common.c: Split off 40x cases from ppc_jumbo_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 64/72] target/ppc/mmu_common.c: Transform ppc_jumbo_xlate() into ppc_6xx_xlate() Nicholas Piggin
2024-05-23 23:07 ` [PULL 65/72] target/ppc/mmu_common.c: Move mmu_ctx_t type to mmu_common.c Nicholas Piggin
2024-05-23 23:07 ` [PULL 66/72] target/ppc: Remove id_tlbs flag from CPU env Nicholas Piggin
2024-05-23 23:07 ` [PULL 67/72] target/ppc: Split off common embedded TLB init Nicholas Piggin
2024-05-23 23:07 ` [PULL 68/72] target/ppc/mmu-hash32.c: Drop a local variable Nicholas Piggin
2024-05-23 23:07 ` [PULL 69/72] target/ppc/mmu-radix64.c: " Nicholas Piggin
2024-05-23 23:07 ` [PULL 70/72] target/ppc: Add a function to check for page protection bit Nicholas Piggin
2024-05-23 23:07 ` [PULL 71/72] target/ppc: Move out BookE and related MMU functions from mmu_common.c Nicholas Piggin
2024-05-23 23:07 ` [PULL 72/72] target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() Nicholas Piggin
2024-05-23 23:31 ` [PULL 00/72] ppc-for-9.1-1 queue Nicholas Piggin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240523230747.45703-4-npiggin@gmail.com \
--to=npiggin@gmail.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).