From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Caleb Schlossin" <calebs@linux.vnet.ibm.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
qemu-devel@nongnu.org
Subject: [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit
Date: Sun, 26 May 2024 22:26:01 +1000 [thread overview]
Message-ID: <20240526122612.473476-1-npiggin@gmail.com> (raw)
Primary motivation for this series is to improve big-core support.
Other things like SPR indirect, timebase state, PC xscom, are required
for minimal big core support.
I'm still not 100% happy with the big-core topology model after this.
Maybe one day we add pnv big core and pnv small core structures. But
nothing is completely clean because big core mode still has certain
small core restrictions. I think for now we take a bit of mostly
abstracted ugliness in TCG code for the benefit of not spreading
hacks through pervasive (xscom) core addressing.
After this series, power9 and power10 get through skiboot/Linux boot
in SMT8 big-core mode. Not all big core registers are modeled
exactly (some are not shared between small core halves), but that
mostly doesn't matter for OPAL and it can be improved later.
Thanks,
Nick
Nicholas Piggin (10):
ppc/pnv: Add pointer from PnvCPUState to PnvCore
ppc/pnv: Move timebase state into PnvCore
target/ppc: Improve SPR indirect registers
ppc/pnv: specialise init for powernv8/9/10 machines
ppc/pnv: Extend chip_pir class method to TIR as well
ppc: Add a core_index to CPUPPCState for SMT vCPUs
target/ppc: Add helpers to check for SMT sibling threads
ppc/pnv: Invert the design for big-core machine modelling
ppc/pnv: Implement POWER10 PC xscom registers for direct controls
ppc/pnv: Add an LPAR per core machine option
include/hw/core/cpu.h | 8 +
include/hw/ppc/pnv.h | 6 +
include/hw/ppc/pnv_chip.h | 3 +-
include/hw/ppc/pnv_core.h | 31 ++++
target/ppc/cpu.h | 37 ++---
hw/ppc/pnv.c | 297 ++++++++++++++++++++++++++++-------
hw/ppc/pnv_chiptod.c | 6 +-
hw/ppc/pnv_core.c | 129 +++++++++++++--
hw/ppc/spapr_cpu_core.c | 7 +
system/cpus.c | 10 ++
target/ppc/cpu_init.c | 26 +--
target/ppc/excp_helper.c | 16 +-
target/ppc/misc_helper.c | 98 ++++++------
target/ppc/timebase_helper.c | 82 +++++-----
14 files changed, 548 insertions(+), 208 deletions(-)
--
2.43.0
next reply other threads:[~2024-05-26 12:28 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-26 12:26 Nicholas Piggin [this message]
2024-05-26 12:26 ` [RFC PATCH 01/10] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-05-27 15:23 ` Cédric Le Goater
2024-05-28 6:19 ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 02/10] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-05-28 6:28 ` Harsh Prateek Bora
2024-05-28 7:52 ` Cédric Le Goater
2024-05-29 0:19 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers Nicholas Piggin
2024-05-28 6:50 ` Harsh Prateek Bora
2024-05-29 0:13 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 04/10] ppc/pnv: specialise init for powernv8/9/10 machines Nicholas Piggin
2024-05-28 7:10 ` Harsh Prateek Bora
2024-05-28 7:45 ` Cédric Le Goater
2024-05-29 0:18 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-05-28 8:32 ` Harsh Prateek Bora
2024-05-29 0:24 ` Nicholas Piggin
2024-05-29 6:30 ` Cédric Le Goater
2024-05-30 6:38 ` Nicholas Piggin
2024-05-30 6:42 ` Cédric Le Goater
2024-05-26 12:26 ` [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-05-28 8:48 ` Harsh Prateek Bora
2024-05-28 8:52 ` Harsh Prateek Bora
2024-05-29 0:28 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-05-28 9:16 ` Harsh Prateek Bora
2024-05-29 0:31 ` Nicholas Piggin
2024-05-29 6:34 ` Cédric Le Goater
2024-05-30 6:38 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 08/10] ppc/pnv: Invert the design for big-core machine modelling Nicholas Piggin
2024-05-29 6:57 ` Cédric Le Goater
2024-05-30 6:52 ` Nicholas Piggin
2024-05-30 7:46 ` Cédric Le Goater
2024-06-03 5:22 ` Nicholas Piggin
2024-05-29 10:49 ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 09/10] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-05-29 7:00 ` Cédric Le Goater
2024-05-30 6:53 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 10/10] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-05-29 7:02 ` Cédric Le Goater
2024-05-27 6:25 ` [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Cédric Le Goater
2024-05-27 7:32 ` Nicholas Piggin
2024-05-27 7:36 ` Cédric Le Goater
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