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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	"Caleb Schlossin" <calebs@linux.vnet.ibm.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Frédéric Barrat" <fbarrat@linux.ibm.com>,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	qemu-devel@nongnu.org
Subject: [RFC PATCH 04/10] ppc/pnv: specialise init for powernv8/9/10 machines
Date: Sun, 26 May 2024 22:26:05 +1000	[thread overview]
Message-ID: <20240526122612.473476-5-npiggin@gmail.com> (raw)
In-Reply-To: <20240526122612.473476-1-npiggin@gmail.com>

This will allow different settings and checks for different
machine types with later changes.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/ppc/pnv.c | 35 ++++++++++++++++++++++++++++++-----
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6e3a5ccdec..a706de2e36 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -976,11 +976,6 @@ static void pnv_init(MachineState *machine)
     pnv->num_chips =
         machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
 
-    if (machine->smp.threads > 8) {
-        error_report("Cannot support more than 8 threads/core "
-                     "on a powernv machine");
-        exit(1);
-    }
     if (!is_power_of_2(machine->smp.threads)) {
         error_report("Cannot support %d threads/core on a powernv"
                      "machine because it must be a power of 2",
@@ -1076,6 +1071,33 @@ static void pnv_init(MachineState *machine)
     }
 }
 
+static void pnv_power8_init(MachineState *machine)
+{
+    if (machine->smp.threads > 8) {
+        error_report("Cannot support more than 8 threads/core "
+                     "on a powernv POWER8 machine");
+        exit(1);
+    }
+
+    pnv_init(machine);
+}
+
+static void pnv_power9_init(MachineState *machine)
+{
+    if (machine->smp.threads > 8) {
+        error_report("Cannot support more than 8 threads/core "
+                     "on a powernv9/10 machine");
+        exit(1);
+    }
+
+    pnv_init(machine);
+}
+
+static void pnv_power10_init(MachineState *machine)
+{
+    pnv_power9_init(machine);
+}
+
 /*
  *    0:21  Reserved - Read as zeros
  *   22:24  Chip ID
@@ -2423,6 +2445,7 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
     };
 
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
+    mc->init = pnv_power8_init;
     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
     compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
 
@@ -2449,6 +2472,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
     };
 
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
+    mc->init = pnv_power9_init;
     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2");
     compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
 
@@ -2473,6 +2497,7 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
         { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
     };
 
+    mc->init = pnv_power10_init;
     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
     compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
 
-- 
2.43.0



  parent reply	other threads:[~2024-05-26 12:27 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-26 12:26 [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 01/10] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-05-27 15:23   ` Cédric Le Goater
2024-05-28  6:19   ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 02/10] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-05-28  6:28   ` Harsh Prateek Bora
2024-05-28  7:52     ` Cédric Le Goater
2024-05-29  0:19       ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers Nicholas Piggin
2024-05-28  6:50   ` Harsh Prateek Bora
2024-05-29  0:13     ` Nicholas Piggin
2024-05-26 12:26 ` Nicholas Piggin [this message]
2024-05-28  7:10   ` [RFC PATCH 04/10] ppc/pnv: specialise init for powernv8/9/10 machines Harsh Prateek Bora
2024-05-28  7:45     ` Cédric Le Goater
2024-05-29  0:18       ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-05-28  8:32   ` Harsh Prateek Bora
2024-05-29  0:24     ` Nicholas Piggin
2024-05-29  6:30       ` Cédric Le Goater
2024-05-30  6:38         ` Nicholas Piggin
2024-05-30  6:42           ` Cédric Le Goater
2024-05-26 12:26 ` [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-05-28  8:48   ` Harsh Prateek Bora
2024-05-28  8:52     ` Harsh Prateek Bora
2024-05-29  0:28       ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-05-28  9:16   ` Harsh Prateek Bora
2024-05-29  0:31     ` Nicholas Piggin
2024-05-29  6:34   ` Cédric Le Goater
2024-05-30  6:38     ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 08/10] ppc/pnv: Invert the design for big-core machine modelling Nicholas Piggin
2024-05-29  6:57   ` Cédric Le Goater
2024-05-30  6:52     ` Nicholas Piggin
2024-05-30  7:46       ` Cédric Le Goater
2024-06-03  5:22         ` Nicholas Piggin
2024-05-29 10:49   ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 09/10] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-05-29  7:00   ` Cédric Le Goater
2024-05-30  6:53     ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 10/10] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-05-29  7:02   ` Cédric Le Goater
2024-05-27  6:25 ` [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Cédric Le Goater
2024-05-27  7:32   ` Nicholas Piggin
2024-05-27  7:36     ` Cédric Le Goater

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