From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk
Subject: [PATCH v2 20/37] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS
Date: Sun, 26 May 2024 12:42:37 -0700 [thread overview]
Message-ID: <20240526194254.459395-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/helper.h | 2 ++
target/sparc/insns.decode | 9 +++++++++
target/sparc/translate.c | 11 +++++++++++
target/sparc/vis_helper.c | 36 ++++++++++++++++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index ed295c01e0..219f0e04c7 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -119,6 +119,8 @@ DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmean16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fslas16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fslas32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#define VIS_CMPHELPER(name) \
DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 295fc36128..a5eefebfbc 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -408,6 +408,15 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d
FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d
+ FSLL16 10 ..... 110110 ..... 0 0010 0001 ..... @d_d_d
+ FSRL16 10 ..... 110110 ..... 0 0010 0011 ..... @d_d_d
+ FSLAS16 10 ..... 110110 ..... 0 0010 1001 ..... @d_d_d
+ FSRA16 10 ..... 110110 ..... 0 0010 1011 ..... @d_d_d
+ FSLL32 10 ..... 110110 ..... 0 0010 0101 ..... @d_d_d
+ FSRL32 10 ..... 110110 ..... 0 0010 0111 ..... @d_d_d
+ FSLAS32 10 ..... 110110 ..... 0 0010 1101 ..... @d_d_d
+ FSRA32 10 ..... 110110 ..... 0 0010 1111 ..... @d_d_d
+
FPCMPULE8 10 ..... 110110 ..... 1 0010 0000 ..... @r_d_d
FPCMPUGT8 10 ..... 110110 ..... 1 0010 1000 ..... @r_d_d
FPCMPNE8 10 ..... 110110 ..... 1 0010 0010 ..... @r_d_d
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 7a20e79b7e..ade9df3960 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -83,6 +83,8 @@
# define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; })
+# define gen_helper_fslas16 ({ qemu_build_not_reached(); NULL; })
+# define gen_helper_fslas32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fstox ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL; })
@@ -4957,6 +4959,13 @@ TRANS(FPADDS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_ssadd)
TRANS(FPSUBS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sssub)
TRANS(FPSUBS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sssub)
+TRANS(FSLL16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_shlv)
+TRANS(FSLL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_shlv)
+TRANS(FSRL16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_shrv)
+TRANS(FSRL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_shrv)
+TRANS(FSRA16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sarv)
+TRANS(FSRA32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sarv)
+
static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
{
@@ -4996,6 +5005,8 @@ TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd)
TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64)
TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64)
+TRANS(FSLAS16, VIS3, do_ddd, a, gen_helper_fslas16)
+TRANS(FSLAS32, VIS3, do_ddd, a, gen_helper_fslas32)
static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv, TCGv_i64, TCGv_i64))
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
index 5a5da17132..c21522c533 100644
--- a/target/sparc/vis_helper.c
+++ b/target/sparc/vis_helper.c
@@ -473,3 +473,39 @@ uint64_t helper_fmean16(uint64_t src1, uint64_t src2)
return r.ll;
}
+
+uint64_t helper_fslas16(uint64_t src1, uint64_t src2)
+{
+ VIS64 r, s1, s2;
+
+ s1.ll = src1;
+ s2.ll = src2;
+ r.ll = 0;
+
+ for (int i = 0; i < 4; ++i) {
+ int t = s1.VIS_SW64(i) << (s2.VIS_W64(i) % 16);
+ t = MIN(t, INT16_MAX);
+ t = MAX(t, INT16_MIN);
+ r.VIS_SW64(i) = t;
+ }
+
+ return r.ll;
+}
+
+uint64_t helper_fslas32(uint64_t src1, uint64_t src2)
+{
+ VIS64 r, s1, s2;
+
+ s1.ll = src1;
+ s2.ll = src2;
+ r.ll = 0;
+
+ for (int i = 0; i < 2; ++i) {
+ int64_t t = (int64_t)(int32_t)s1.VIS_L64(i) << (s2.VIS_L64(i) % 32);
+ t = MIN(t, INT32_MAX);
+ t = MAX(t, INT32_MIN);
+ r.VIS_L64(i) = t;
+ }
+
+ return r.ll;
+}
--
2.34.1
next prev parent reply other threads:[~2024-05-26 19:44 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-26 19:42 [PATCH v2 00/37] target/sparc: Implement VIS4 Richard Henderson
2024-05-26 19:42 ` [PATCH v2 01/37] target/sparc: Fix ARRAY8 Richard Henderson
2024-05-26 19:42 ` [PATCH v2 02/37] target/sparc: Rewrite gen_edge Richard Henderson
2024-05-26 19:42 ` [PATCH v2 03/37] target/sparc: Fix do_dc Richard Henderson
2024-06-04 11:41 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 04/37] target/sparc: Fix helper_fmul8ulx16 Richard Henderson
2024-05-26 19:42 ` [PATCH v2 05/37] target/sparc: Perform DFPREG/QFPREG in decodetree Richard Henderson
2024-05-26 19:42 ` [PATCH v2 06/37] target/sparc: Remove gen_dest_fpr_D Richard Henderson
2024-05-26 19:42 ` [PATCH v2 07/37] target/sparc: Remove cpu_fpr[] Richard Henderson
2024-05-26 19:42 ` [PATCH v2 08/37] target/sparc: Use gvec for VIS1 parallel add/sub Richard Henderson
2024-06-04 13:18 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 09/37] target/sparc: Implement FMAf extension Richard Henderson
2024-05-26 19:42 ` [PATCH v2 10/37] target/sparc: Add feature bits for VIS 3 Richard Henderson
2024-05-26 19:42 ` [PATCH v2 11/37] target/sparc: Implement ADDXC, ADDXCcc Richard Henderson
2024-05-26 19:42 ` [PATCH v2 12/37] target/sparc: Implement CMASK instructions Richard Henderson
2024-06-04 13:30 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 13/37] target/sparc: Implement FCHKSM16 Richard Henderson
2024-06-05 8:07 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 14/37] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL Richard Henderson
2024-05-26 19:42 ` [PATCH v2 15/37] target/sparc: Implement FLCMP Richard Henderson
2024-05-26 19:42 ` [PATCH v2 16/37] target/sparc: Implement FMEAN16 Richard Henderson
2024-06-04 13:33 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 17/37] target/sparc: Implement FPADD64, FPSUB64 Richard Henderson
2024-05-26 19:42 ` [PATCH v2 18/37] target/sparc: Implement FPADDS, FPSUBS Richard Henderson
2024-06-05 8:04 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 19/37] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 Richard Henderson
2024-06-05 7:57 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` Richard Henderson [this message]
2024-06-04 13:38 ` [PATCH v2 20/37] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 21/37] target/sparc: Implement LDXEFSR Richard Henderson
2024-06-05 7:55 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 22/37] target/sparc: Implement LZCNT Richard Henderson
2024-05-26 19:42 ` [PATCH v2 23/37] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd Richard Henderson
2024-06-05 7:49 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 24/37] target/sparc: Implement PDISTN Richard Henderson
2024-05-26 19:42 ` [PATCH v2 25/37] target/sparc: Implement UMULXHI Richard Henderson
2024-06-04 13:40 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 26/37] target/sparc: Implement XMULX Richard Henderson
2024-06-04 13:41 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 27/37] target/sparc: Enable VIS3 feature bit Richard Henderson
2024-06-04 13:42 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 28/37] target/sparc: Implement IMA extension Richard Henderson
2024-05-26 19:42 ` [PATCH v2 29/37] target/sparc: Add feature bit for VIS4 Richard Henderson
2024-05-26 19:42 ` [PATCH v2 30/37] target/sparc: Implement FALIGNDATAi Richard Henderson
2024-06-05 7:35 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 31/37] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS Richard Henderson
2024-05-26 19:42 ` [PATCH v2 32/37] target/sparc: Implement VIS4 comparisons Richard Henderson
2024-06-05 7:10 ` Philippe Mathieu-Daudé
2024-05-26 19:42 ` [PATCH v2 33/37] target/sparc: Implement FPMIN, FPMAX Richard Henderson
2024-05-26 19:42 ` [PATCH v2 34/37] target/sparc: Implement SUBXC, SUBXCcc Richard Henderson
2024-05-26 19:42 ` [PATCH v2 35/37] target/sparc: Implement MWAIT Richard Henderson
2024-06-05 7:27 ` Philippe Mathieu-Daudé
2024-06-05 16:11 ` Richard Henderson
2024-05-26 19:42 ` [PATCH v2 36/37] target/sparc: Implement monitor ASIs Richard Henderson
2024-05-26 19:42 ` [PATCH v2 37/37] target/sparc: Enable VIS4 feature bit Richard Henderson
2024-05-28 21:29 ` [PATCH v2 00/37] target/sparc: Implement VIS4 Mark Cave-Ayland
2024-06-04 6:25 ` Mark Cave-Ayland
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