From: Aditya Gupta <adityag@linux.ibm.com>
To: "Mahesh J Salgaonkar" <mahesh@linux.ibm.com>,
"Madhavan Srinivasan" <maddy@linux.ibm.com>,
"Nicholas Piggin" <npiggin@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
"David Gibson" <david@gibson.dropbear.id.au>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>
Subject: [PATCH v3 02/11] ppc/pseries: Add Power11 cpu type
Date: Mon, 27 May 2024 12:40:33 +0530 [thread overview]
Message-ID: <20240527071042.489540-3-adityag@linux.ibm.com> (raw)
In-Reply-To: <20240527071042.489540-1-adityag@linux.ibm.com>
Add sPAPR CPU Core definition for Power11
Cc: David Gibson <david@gibson.dropbear.id.au> (reviewer:sPAPR (pseries))
Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> (reviewer:sPAPR (pseries))
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
docs/system/ppc/pseries.rst | 6 +++---
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..3277564b34c2 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -15,9 +15,9 @@ Supported devices
=================
* Multi processor support for many Power processors generations: POWER7,
- POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
- but its state is unknown.
- * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
+ POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+
+ exists, but its state is unknown.
+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11)
* vPHB PCIe Host bridge.
* vscsi and vnet devices, compatible with the same devices available on a
PowerVM hypervisor with VIOS managing LPARs.
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index e7c9edd033c8..62416b7e0a7e 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
+ DEFINE_SPAPR_CPU_CORE_TYPE("power11_v2.0"),
#ifdef CONFIG_KVM
DEFINE_SPAPR_CPU_CORE_TYPE("host"),
#endif
--
2.45.1
next prev parent reply other threads:[~2024-05-27 7:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-27 7:10 [PATCH v3 00/11] Power11 support for QEMU Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 01/11] ppc: Add Power11 DD2.0 processor Aditya Gupta
2024-05-27 7:10 ` Aditya Gupta [this message]
2024-05-27 7:10 ` [PATCH v3 03/11] target/ppc: Introduce 'PowerPCCPUClass::logical_pvr' Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 04/11] target/ppc: Fix regression due to Power10 and Power11 having same PCR Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 05/11] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine Aditya Gupta
2024-05-27 15:15 ` Cédric Le Goater
2024-05-28 6:08 ` Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 06/11] ppc/pnv: Add HOMER for POWER11 Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 07/11] ppc/pnv: Add a LPC controller " Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 08/11] ppc/pnv: Add OCC for Power11 Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 09/11] ppc/pnv: Add a PSI bridge model " Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 10/11] ppc/pnv: Add SBE " Aditya Gupta
2024-05-27 7:10 ` [PATCH v3 11/11] ppc/pnv: Update skiboot.lid to support Power11 Aditya Gupta
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