[PATCH 0/6] host/i386: require x86-64-v2 ISA

[PATCH 0/6] host/i386: require x86-64-v2 ISA

[Paolo Bonzini]

x86-64-v2 processors were released in 2008, assume that we have one.
This provides CMOV on 32-bit processors, and also POPCNT and various
vector ISA extensions.

Paolo

Paolo Bonzini (6):
  host/i386: nothing looks at CPUINFO_SSE4
  meson: assume x86-64-v2 baseline ISA
  host/i386: assume presence of CMOV
  host/i386: assume presence of SSE2
  host/i386: assume presence of SSSE3
  host/i386: assume presence of POPCNT

 meson.build                      | 10 +++++++---
 host/include/i386/host/cpuinfo.h |  4 ----
 tcg/i386/tcg-target.h            |  5 ++---
 util/bufferiszero.c              |  2 +-
 util/cpuinfo-i386.c              |  8 ++------
 tcg/i386/tcg-target.c.inc        | 15 +--------------
 6 files changed, 13 insertions(+), 31 deletions(-)

-- 
2.45.1

[PATCH 1/6] host/i386: nothing looks at CPUINFO_SSE4

[Paolo Bonzini]

The only user was the SSE4.1 variant of buffer_is_zero, which has
been removed; code to compute CPUINFO_SSE4 is dead.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 host/include/i386/host/cpuinfo.h | 1 -
 util/cpuinfo-i386.c              | 1 -
 2 files changed, 2 deletions(-)

diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpuinfo.h
index b89e6d2e55a..9386c749881 100644
--- a/host/include/i386/host/cpuinfo.h
+++ b/host/include/i386/host/cpuinfo.h
@@ -16,7 +16,6 @@
 #define CPUINFO_BMI1            (1u << 5)
 #define CPUINFO_BMI2            (1u << 6)
 #define CPUINFO_SSE2            (1u << 7)
-#define CPUINFO_SSE4            (1u << 8)
 #define CPUINFO_AVX1            (1u << 9)
 #define CPUINFO_AVX2            (1u << 10)
 #define CPUINFO_AVX512F         (1u << 11)
diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c
index 9fddb18303d..18ab747a6d2 100644
--- a/util/cpuinfo-i386.c
+++ b/util/cpuinfo-i386.c
@@ -36,7 +36,6 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
 
         info |= (d & bit_CMOV ? CPUINFO_CMOV : 0);
         info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0);
-        info |= (c & bit_SSE4_1 ? CPUINFO_SSE4 : 0);
         info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0);
         info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
         info |= (c & bit_PCLMUL ? CPUINFO_PCLMUL : 0);
-- 
2.45.1

[PATCH 2/6] meson: assume x86-64-v2 baseline ISA

[Paolo Bonzini]

x86-64-v2 processors were released in 2008, assume that we have one.
Unfortunately there is no GCC flag to enable all the features
without disabling what came after; so enable them one by one.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 meson.build | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/meson.build b/meson.build
index 63866071445..19d1fc1f33b 100644
--- a/meson.build
+++ b/meson.build
@@ -336,9 +336,13 @@ if host_arch == 'i386' and not cc.links('''
   qemu_common_flags = ['-march=i486'] + qemu_common_flags
 endif
 
-# ??? Only extremely old AMD cpus do not have cmpxchg16b.
-# If we truly care, we should simply detect this case at
-# runtime and generate the fallback to serial emulation.
+# Assume x86-64-v2 (minus CMPXCHG16B for 32-bit code)
+if host_arch == 'i386'
+  qemu_common_flags = ['-mfpmath=sse'] + qemu_common_flags
+endif
+if host_arch in ['i386', 'x86_64']
+  qemu_common_flags = ['-mpopcnt', '-msse4.2'] + qemu_common_flags
+endif
 if host_arch == 'x86_64'
   qemu_common_flags = ['-mcx16'] + qemu_common_flags
 endif
-- 
2.45.1

[PATCH 3/6] host/i386: assume presence of CMOV

[Paolo Bonzini]

QEMU now requires an x86-64-v2 host, which always has CMOV.
Use it freely in TCG generated code.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 host/include/i386/host/cpuinfo.h |  1 -
 util/cpuinfo-i386.c              |  1 -
 tcg/i386/tcg-target.c.inc        | 15 +--------------
 3 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpuinfo.h
index 9386c749881..81771733eaa 100644
--- a/host/include/i386/host/cpuinfo.h
+++ b/host/include/i386/host/cpuinfo.h
@@ -9,7 +9,6 @@
 /* Digested version of <cpuid.h> */
 
 #define CPUINFO_ALWAYS          (1u << 0)  /* so cpuinfo is nonzero */
-#define CPUINFO_CMOV            (1u << 1)
 #define CPUINFO_MOVBE           (1u << 2)
 #define CPUINFO_LZCNT           (1u << 3)
 #define CPUINFO_POPCNT          (1u << 4)
diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c
index 18ab747a6d2..90f92a42dc8 100644
--- a/util/cpuinfo-i386.c
+++ b/util/cpuinfo-i386.c
@@ -34,7 +34,6 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
     if (max >= 1) {
         __cpuid(1, a, b, c, d);
 
-        info |= (d & bit_CMOV ? CPUINFO_CMOV : 0);
         info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0);
         info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0);
         info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 59235b4f387..9a54ef7f8db 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -157,12 +157,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
 #define SOFTMMU_RESERVE_REGS \
     (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0)
 
-/* For 64-bit, we always know that CMOV is available.  */
-#if TCG_TARGET_REG_BITS == 64
-# define have_cmov      true
-#else
-# define have_cmov      (cpuinfo & CPUINFO_CMOV)
-#endif
 #define have_bmi2       (cpuinfo & CPUINFO_BMI2)
 #define have_lzcnt      (cpuinfo & CPUINFO_LZCNT)
 
@@ -1815,14 +1809,7 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
 static void tcg_out_cmov(TCGContext *s, int jcc, int rexw,
                          TCGReg dest, TCGReg v1)
 {
-    if (have_cmov) {
-        tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1);
-    } else {
-        TCGLabel *over = gen_new_label();
-        tcg_out_jxx(s, jcc ^ 1, over, 1);
-        tcg_out_mov(s, TCG_TYPE_I32, dest, v1);
-        tcg_out_label(s, over);
-    }
+    tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1);
 }
 
 static void tcg_out_movcond(TCGContext *s, int rexw, TCGCond cond,
-- 
2.45.1

[PATCH 4/6] host/i386: assume presence of SSE2

[Paolo Bonzini]

QEMU now requires an x86-64-v2 host, which has SSE2.
Use it freely in buffer_is_zero.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 host/include/i386/host/cpuinfo.h | 1 -
 util/bufferiszero.c              | 2 +-
 util/cpuinfo-i386.c              | 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpuinfo.h
index 81771733eaa..72f6fad61e5 100644
--- a/host/include/i386/host/cpuinfo.h
+++ b/host/include/i386/host/cpuinfo.h
@@ -14,7 +14,6 @@
 #define CPUINFO_POPCNT          (1u << 4)
 #define CPUINFO_BMI1            (1u << 5)
 #define CPUINFO_BMI2            (1u << 6)
-#define CPUINFO_SSE2            (1u << 7)
 #define CPUINFO_AVX1            (1u << 9)
 #define CPUINFO_AVX2            (1u << 10)
 #define CPUINFO_AVX512F         (1u << 11)
diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index 74864f7b782..6245976eca1 100644
--- a/util/bufferiszero.c
+++ b/util/bufferiszero.c
@@ -195,7 +195,7 @@ static unsigned best_accel(void)
         return 2;
     }
 #endif
-    return info & CPUINFO_SSE2 ? 1 : 0;
+    return 1;
 }
 
 #elif defined(__aarch64__) && defined(__ARM_NEON)
diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c
index 90f92a42dc8..ca74ef04f54 100644
--- a/util/cpuinfo-i386.c
+++ b/util/cpuinfo-i386.c
@@ -34,7 +34,6 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
     if (max >= 1) {
         __cpuid(1, a, b, c, d);
 
-        info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0);
         info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0);
         info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
         info |= (c & bit_PCLMUL ? CPUINFO_PCLMUL : 0);
-- 
2.45.1

[PATCH 5/6] host/i386: assume presence of SSSE3

[Paolo Bonzini]

QEMU now requires an x86-64-v2 host, which has SSSE3 instructions
(notably, PSHUFB which is used by QEMU's AES implementation).
Do not bother checking it.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 util/cpuinfo-i386.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c
index ca74ef04f54..b413075b9f2 100644
--- a/util/cpuinfo-i386.c
+++ b/util/cpuinfo-i386.c
@@ -38,8 +38,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
         info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
         info |= (c & bit_PCLMUL ? CPUINFO_PCLMUL : 0);
 
-        /* Our AES support requires PSHUFB as well. */
-        info |= ((c & bit_AES) && (c & bit_SSSE3) ? CPUINFO_AES : 0);
+        /* NOTE: our AES support requires SSSE3 (PSHUFB) as well. */
+        info |= (c & bit_AES) ? CPUINFO_AES : 0;
 
         /* For AVX features, we must check available and usable. */
         if ((c & bit_AVX) && (c & bit_OSXSAVE)) {
-- 
2.45.1

[PATCH 6/6] host/i386: assume presence of POPCNT

[Paolo Bonzini]

QEMU now requires an x86-64-v2 host, which has the POPCNT instruction.
Use it freely in TCG-generated code.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 host/include/i386/host/cpuinfo.h | 1 -
 tcg/i386/tcg-target.h            | 5 ++---
 util/cpuinfo-i386.c              | 1 -
 3 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpuinfo.h
index 72f6fad61e5..c1e94d75ce1 100644
--- a/host/include/i386/host/cpuinfo.h
+++ b/host/include/i386/host/cpuinfo.h
@@ -11,7 +11,6 @@
 #define CPUINFO_ALWAYS          (1u << 0)  /* so cpuinfo is nonzero */
 #define CPUINFO_MOVBE           (1u << 2)
 #define CPUINFO_LZCNT           (1u << 3)
-#define CPUINFO_POPCNT          (1u << 4)
 #define CPUINFO_BMI1            (1u << 5)
 #define CPUINFO_BMI2            (1u << 6)
 #define CPUINFO_AVX1            (1u << 9)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 2f67a97e059..ecc69827287 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -111,7 +111,6 @@ typedef enum {
 #endif
 
 #define have_bmi1         (cpuinfo & CPUINFO_BMI1)
-#define have_popcnt       (cpuinfo & CPUINFO_POPCNT)
 #define have_avx1         (cpuinfo & CPUINFO_AVX1)
 #define have_avx2         (cpuinfo & CPUINFO_AVX2)
 #define have_movbe        (cpuinfo & CPUINFO_MOVBE)
@@ -143,7 +142,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nor_i32          0
 #define TCG_TARGET_HAS_clz_i32          1
 #define TCG_TARGET_HAS_ctz_i32          1
-#define TCG_TARGET_HAS_ctpop_i32        have_popcnt
+#define TCG_TARGET_HAS_ctpop_i32        1
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_extract_i32      1
 #define TCG_TARGET_HAS_sextract_i32     1
@@ -178,7 +177,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nor_i64          0
 #define TCG_TARGET_HAS_clz_i64          1
 #define TCG_TARGET_HAS_ctz_i64          1
-#define TCG_TARGET_HAS_ctpop_i64        have_popcnt
+#define TCG_TARGET_HAS_ctpop_i64        1
 #define TCG_TARGET_HAS_deposit_i64      1
 #define TCG_TARGET_HAS_extract_i64      1
 #define TCG_TARGET_HAS_sextract_i64     0
diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c
index b413075b9f2..883dfa4dd95 100644
--- a/util/cpuinfo-i386.c
+++ b/util/cpuinfo-i386.c
@@ -35,7 +35,6 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
         __cpuid(1, a, b, c, d);
 
         info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0);
-        info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
         info |= (c & bit_PCLMUL ? CPUINFO_PCLMUL : 0);
 
         /* NOTE: our AES support requires SSSE3 (PSHUFB) as well. */
-- 
2.45.1

Re: [PATCH 1/6] host/i386: nothing looks at CPUINFO_SSE4

[Philippe Mathieu-Daudé]

On 31/5/24 11:14, Paolo Bonzini wrote:
> The only user was the SSE4.1 variant of buffer_is_zero, which has
> been removed; code to compute CPUINFO_SSE4 is dead.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   host/include/i386/host/cpuinfo.h | 1 -
>   util/cpuinfo-i386.c              | 1 -
>   2 files changed, 2 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH 0/6] host/i386: require x86-64-v2 ISA

[Richard Henderson]

On 5/31/24 02:14, Paolo Bonzini wrote:
> Paolo Bonzini (6):
>    host/i386: nothing looks at CPUINFO_SSE4
>    meson: assume x86-64-v2 baseline ISA
>    host/i386: assume presence of CMOV
>    host/i386: assume presence of SSE2
>    host/i386: assume presence of SSSE3
>    host/i386: assume presence of POPCNT

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 1/6] host/i386: nothing looks at CPUINFO_SSE4

[Zhao Liu]

On Fri, May 31, 2024 at 11:14:52AM +0200, Paolo Bonzini wrote:
> Date: Fri, 31 May 2024 11:14:52 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH 1/6] host/i386: nothing looks at CPUINFO_SSE4
> X-Mailer: git-send-email 2.45.1
> 
> The only user was the SSE4.1 variant of buffer_is_zero, which has
> been removed; code to compute CPUINFO_SSE4 is dead.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  host/include/i386/host/cpuinfo.h | 1 -
>  util/cpuinfo-i386.c              | 1 -
>  2 files changed, 2 deletions(-)
>

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH 3/6] host/i386: assume presence of CMOV

[Zhao Liu]

On Fri, May 31, 2024 at 11:14:54AM +0200, Paolo Bonzini wrote:
> Date: Fri, 31 May 2024 11:14:54 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH 3/6] host/i386: assume presence of CMOV
> X-Mailer: git-send-email 2.45.1
> 
> QEMU now requires an x86-64-v2 host, which always has CMOV.
> Use it freely in TCG generated code.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  host/include/i386/host/cpuinfo.h |  1 -
>  util/cpuinfo-i386.c              |  1 -
>  tcg/i386/tcg-target.c.inc        | 15 +--------------
>  3 files changed, 1 insertion(+), 16 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
 

Re: [PATCH 4/6] host/i386: assume presence of SSE2

[Zhao Liu]

On Fri, May 31, 2024 at 11:14:55AM +0200, Paolo Bonzini wrote:
> Date: Fri, 31 May 2024 11:14:55 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH 4/6] host/i386: assume presence of SSE2
> X-Mailer: git-send-email 2.45.1
> 
> QEMU now requires an x86-64-v2 host, which has SSE2.
> Use it freely in buffer_is_zero.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  host/include/i386/host/cpuinfo.h | 1 -
>  util/bufferiszero.c              | 2 +-
>  util/cpuinfo-i386.c              | 1 -
>  3 files changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH 5/6] host/i386: assume presence of SSSE3

[Zhao Liu]

On Fri, May 31, 2024 at 11:14:56AM +0200, Paolo Bonzini wrote:
> Date: Fri, 31 May 2024 11:14:56 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH 5/6] host/i386: assume presence of SSSE3
> X-Mailer: git-send-email 2.45.1
> 
> QEMU now requires an x86-64-v2 host, which has SSSE3 instructions
> (notably, PSHUFB which is used by QEMU's AES implementation).
> Do not bother checking it.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  util/cpuinfo-i386.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH 6/6] host/i386: assume presence of POPCNT

[Zhao Liu]

On Fri, May 31, 2024 at 11:14:57AM +0200, Paolo Bonzini wrote:
> Date: Fri, 31 May 2024 11:14:57 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH 6/6] host/i386: assume presence of POPCNT
> X-Mailer: git-send-email 2.45.1
> 
> QEMU now requires an x86-64-v2 host, which has the POPCNT instruction.
> Use it freely in TCG-generated code.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  host/include/i386/host/cpuinfo.h | 1 -
>  tcg/i386/tcg-target.h            | 5 ++---
>  util/cpuinfo-i386.c              | 1 -
>  3 files changed, 2 insertions(+), 5 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH 2/6] meson: assume x86-64-v2 baseline ISA

[Zhao Liu]

On Fri, May 31, 2024 at 11:14:53AM +0200, Paolo Bonzini wrote:
> Date: Fri, 31 May 2024 11:14:53 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH 2/6] meson: assume x86-64-v2 baseline ISA
> X-Mailer: git-send-email 2.45.1
> 
> x86-64-v2 processors were released in 2008, assume that we have one.
> Unfortunately there is no GCC flag to enable all the features
> without disabling what came after; so enable them one by one.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  meson.build | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/meson.build b/meson.build
> index 63866071445..19d1fc1f33b 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -336,9 +336,13 @@ if host_arch == 'i386' and not cc.links('''
>    qemu_common_flags = ['-march=i486'] + qemu_common_flags
>  endif
>  
> -# ??? Only extremely old AMD cpus do not have cmpxchg16b.
> -# If we truly care, we should simply detect this case at
> -# runtime and generate the fallback to serial emulation.
> +# Assume x86-64-v2 (minus CMPXCHG16B for 32-bit code)

Is it necessary to state the requirement (x86-64-v2) for x86 host in
some doc?

e.g., docs/system/target-i386.rst.

> +if host_arch == 'i386'
> +  qemu_common_flags = ['-mfpmath=sse'] + qemu_common_flags
> +endif
> +if host_arch in ['i386', 'x86_64']
> +  qemu_common_flags = ['-mpopcnt', '-msse4.2'] + qemu_common_flags
> +endif
>  if host_arch == 'x86_64'
>    qemu_common_flags = ['-mcx16'] + qemu_common_flags
>  endif
> -- 
> 2.45.1

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH 0/6] host/i386: require x86-64-v2 ISA

[Alexander Monakov]

Hi,

On Fri, 31 May 2024, Paolo Bonzini wrote:

> x86-64-v2 processors were released in 2008, assume that we have one.
> This provides CMOV on 32-bit processors, and also POPCNT and various
> vector ISA extensions.

If my contributions to recent cleanups and speedups for buffer_is_zero
count for something, I'd like to ask you to reconsider. I do not see
what distribution maintainers (where there's no distro-wide switch to
x86_64-v2 baseline happening yet) are supposed to do with SIGILL reports
coming from affected users after this change.

I'm sure it's not "here's a nickel, kid...", but I'm honestly at a loss
what you'd suggest.

Looking at the patches, the gains appear to be so remarkably tiny, with
the exception of adding CMOV to baseline, that I question if it's worth
the friction. Is there something I'm not seeing?

I think basing the decision on when the earliest x86_64-v2 processors appeared
is not right.

Would you consider a reversal of the three patches that bump the baseline
beyond SSE2?

>   meson: assume x86-64-v2 baseline ISA
>   host/i386: assume presence of SSSE3
>   host/i386: assume presence of POPCNT

Thank you.
Alexander