From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: dbarboza@ventanamicro.com, Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: [RFC PATCH v2 4/6] target/riscv: Add check_probe_[read|write] helper functions
Date: Sat, 1 Jun 2024 01:44:51 +0800 [thread overview]
Message-ID: <20240531174504.281461-5-max.chou@sifive.com> (raw)
In-Reply-To: <20240531174504.281461-1-max.chou@sifive.com>
The helper_check_probe_[read|write] functions wrap the probe_pages
function to perform virtual address resolution for continuous vector
load/store instructions.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/helper.h | 4 ++++
target/riscv/vector_helper.c | 12 ++++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index aaf68eadfb7..f4bc907e85f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1,6 +1,10 @@
/* Exceptions */
DEF_HELPER_2(raise_exception, noreturn, env, i32)
+/* Probe page */
+DEF_HELPER_FLAGS_3(check_probe_read, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(check_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)
+
/* Floating Point - rounding mode */
DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cb7267c3217..9263ab26b19 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -136,6 +136,18 @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
}
}
+void HELPER(check_probe_read)(CPURISCVState *env, target_ulong addr,
+ target_ulong len)
+{
+ probe_pages(env, addr, len, GETPC(), MMU_DATA_LOAD);
+}
+
+void HELPER(check_probe_write)(CPURISCVState *env, target_ulong addr,
+ target_ulong len)
+{
+ probe_pages(env, addr, len, GETPC(), MMU_DATA_STORE);
+}
+
static inline void vext_set_elem_mask(void *v0, int index,
uint8_t value)
{
--
2.34.1
next prev parent reply other threads:[~2024-05-31 17:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-31 17:44 [RFC PATCH v2 0/6] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions Max Chou
2024-05-31 17:44 ` [RFC PATCH v2 1/6] target/riscv: Separate vector segment " Max Chou
2024-05-31 17:44 ` [RFC PATCH v2 2/6] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb Max Chou
2024-05-31 17:44 ` [RFC PATCH v2 3/6] target/riscv: Inline vext_ldst_us and corresponding function for performance Max Chou
2024-05-31 17:44 ` Max Chou [this message]
2024-05-31 17:44 ` [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations Max Chou
2024-06-02 17:45 ` Richard Henderson
2024-06-03 15:50 ` Max Chou
2024-06-04 0:58 ` Richard Henderson
2024-05-31 17:44 ` [RFC PATCH v2 6/6] target/riscv: rvv: Optimize vl8re8.v/vs8r.v " Max Chou
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