From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PATCH 19/25] target/i386: convert XADD to new decoder
Date: Sat, 8 Jun 2024 10:41:07 +0200 [thread overview]
Message-ID: <20240608084113.2770363-20-pbonzini@redhat.com> (raw)
In-Reply-To: <20240608084113.2770363-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 35 --------------------------------
target/i386/tcg/decode-new.c.inc | 3 ++-
target/i386/tcg/emit.c.inc | 24 ++++++++++++++++++++++
3 files changed, 26 insertions(+), 36 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index a9cf1332b43..7a63c927c1f 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -818,12 +818,6 @@ static void gen_movs(DisasContext *s, MemOp ot)
gen_op_add_reg(s, s->aflag, R_EDI, dshift);
}
-static void gen_op_update2_cc(DisasContext *s)
-{
- tcg_gen_mov_tl(cpu_cc_src, s->T1);
- tcg_gen_mov_tl(cpu_cc_dst, s->T0);
-}
-
/* compute all eflags to reg */
static void gen_mov_eflags(DisasContext *s, TCGv reg)
{
@@ -3006,35 +3000,6 @@ static void disas_insn_old(DisasContext *s, CPUState *cpu, int b)
switch (b) {
/**************************/
/* arith & logic */
- case 0x1c0:
- case 0x1c1: /* xadd Ev, Gv */
- ot = mo_b_d(b, dflag);
- modrm = x86_ldub_code(env, s);
- reg = ((modrm >> 3) & 7) | REX_R(s);
- mod = (modrm >> 6) & 3;
- gen_op_mov_v_reg(s, ot, s->T0, reg);
- if (mod == 3) {
- rm = (modrm & 7) | REX_B(s);
- gen_op_mov_v_reg(s, ot, s->T1, rm);
- tcg_gen_add_tl(s->T0, s->T0, s->T1);
- gen_op_mov_reg_v(s, ot, reg, s->T1);
- gen_op_mov_reg_v(s, ot, rm, s->T0);
- } else {
- gen_lea_modrm(env, s, modrm);
- if (s->prefix & PREFIX_LOCK) {
- tcg_gen_atomic_fetch_add_tl(s->T1, s->A0, s->T0,
- s->mem_index, ot | MO_LE);
- tcg_gen_add_tl(s->T0, s->T0, s->T1);
- } else {
- gen_op_ld_v(s, ot, s->T1, s->A0);
- tcg_gen_add_tl(s->T0, s->T0, s->T1);
- gen_op_st_v(s, ot, s->T0, s->A0);
- }
- gen_op_mov_reg_v(s, ot, reg, s->T1);
- }
- gen_op_update2_cc(s);
- set_cc_op(s, CC_OP_ADDB + ot);
- break;
case 0x1b0:
case 0x1b1: /* cmpxchg Ev, Gv */
{
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 64ec731bf4a..11ecd1c6c1d 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -1188,6 +1188,8 @@ static const X86OpEntry opcodes_0F[256] = {
[0xb6] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, zextT0), /* MOVZX */
[0xb7] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, zextT0), /* MOVZX */
+ [0xc0] = X86_OP_ENTRY2(XADD, E,b, G,b, lock),
+ [0xc1] = X86_OP_ENTRY2(XADD, E,v, G,v, lock),
[0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0xc3] = X86_OP_ENTRY3(MOV, EM,y,G,y, None,None, cpuid(SSE2)), /* MOVNTI */
[0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
@@ -2611,7 +2613,6 @@ static void disas_insn(DisasContext *s, CPUState *cpu)
case 0x00 ... 0x01: /* mostly privileged instructions */
case 0x1a ... 0x1b: /* MPX */
case 0xb0 ... 0xb1: /* cmpxchg */
- case 0xc0 ... 0xc1: /* xadd */
case 0xc7: /* grp9 */
disas_insn_old(s, cpu, b + 0x100);
return;
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 2fbf2a5ce8c..42e41a7a87c 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -4492,6 +4492,30 @@ static void gen_WRxxBASE(DisasContext *s, X86DecodedInsn *decode)
tcg_gen_mov_tl(base, s->T0);
}
+static void gen_XADD(DisasContext *s, X86DecodedInsn *decode)
+{
+ MemOp ot = decode->op[1].ot;
+
+ decode->cc_dst = tcg_temp_new();
+ decode->cc_src = s->T1;
+ decode->cc_op = CC_OP_ADDB + ot;
+
+ if (s->prefix & PREFIX_LOCK) {
+ tcg_gen_atomic_fetch_add_tl(s->T0, s->A0, s->T1, s->mem_index, ot | MO_LE);
+ tcg_gen_add_tl(decode->cc_dst, s->T0, s->T1);
+ } else {
+ tcg_gen_add_tl(decode->cc_dst, s->T0, s->T1);
+ /*
+ * NOTE: writing memory first is important for MMU exceptions,
+ * but "new result" wins for XADD AX, AX.
+ */
+ gen_writeback(s, decode, 0, decode->cc_dst);
+ }
+ if (decode->op[0].has_ea || decode->op[2].n != decode->op[0].n) {
+ gen_writeback(s, decode, 2, s->T0);
+ }
+}
+
static void gen_XCHG(DisasContext *s, X86DecodedInsn *decode)
{
if (s->prefix & PREFIX_LOCK) {
--
2.45.1
next prev parent reply other threads:[~2024-06-08 8:42 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-08 8:40 [PATCH 00/25] target/i386: more progress towards new decoder Paolo Bonzini
2024-06-08 8:40 ` [PATCH 01/25] target/i386: remove CPUX86State argument from generator functions Paolo Bonzini
2024-06-08 14:47 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 02/25] target/i386: rewrite flags writeback for ADCX/ADOX Paolo Bonzini
2024-06-08 18:05 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 03/25] target/i386: put BLS* input in T1, use generic flag writeback Paolo Bonzini
2024-06-08 18:07 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 04/25] target/i386: change X86_ENTRYr to use T0 Paolo Bonzini
2024-06-08 18:10 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 05/25] target/i386: change X86_ENTRYwr to use T0, use it for moves Paolo Bonzini
2024-06-08 18:13 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 06/25] target/i386: replace NoSeg special with NoLoadEA Paolo Bonzini
2024-06-08 18:16 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 07/25] target/i386: fix processing of intercept 0 (read CR0) Paolo Bonzini
2024-06-08 18:17 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 08/25] target/i386: convert MOV from/to CR and DR to new decoder Paolo Bonzini
2024-06-08 18:24 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 09/25] target/i386: fix bad sorting of entries in the 0F table Paolo Bonzini
2024-06-08 18:26 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 10/25] target/i386: finish converting 0F AE to the new decoder Paolo Bonzini
2024-06-08 18:42 ` Richard Henderson
2024-10-21 1:49 ` Guenter Roeck
2024-10-21 6:57 ` Paolo Bonzini
2024-10-21 13:54 ` Guenter Roeck
2024-06-08 8:40 ` [PATCH 11/25] target/i386: replace read_crN helper with read_cr8 Paolo Bonzini
2024-06-08 18:45 ` Richard Henderson
2024-06-10 17:14 ` Paolo Bonzini
2024-06-08 8:41 ` [PATCH 12/25] target/i386: split X86_CHECK_prot into PE and VM86 checks Paolo Bonzini
2024-06-08 18:47 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 13/25] target/i386: convert non-grouped, helper-based 2-byte opcodes Paolo Bonzini
2024-06-08 19:03 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 14/25] target/i386: convert bit test instructions to new decoder Paolo Bonzini
2024-06-08 19:37 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 15/25] target/i386: pull load/writeback out of gen_shiftd_rm_T1 Paolo Bonzini
2024-06-08 19:39 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 16/25] target/i386: adapt gen_shift_count for SHLD/SHRD Paolo Bonzini
2024-06-08 19:42 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 17/25] target/i386: convert SHLD/SHRD to new decoder Paolo Bonzini
2024-06-08 19:47 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 18/25] target/i386: convert LZCNT/TZCNT/BSF/BSR/POPCNT " Paolo Bonzini
2024-06-08 19:53 ` Richard Henderson
2024-06-08 8:41 ` Paolo Bonzini [this message]
2024-06-08 20:00 ` [PATCH 19/25] target/i386: convert XADD " Richard Henderson
2024-06-08 8:41 ` [PATCH 20/25] target/i386: convert CMPXCHG " Paolo Bonzini
2024-06-08 20:04 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 21/25] target/i386: decode address before going back to translate.c Paolo Bonzini
2024-06-08 20:13 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 22/25] target/i386: list instructions still in translate.c Paolo Bonzini
2024-06-08 20:14 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 23/25] target/i386: assert that cc_op* and pc_save are preserved Paolo Bonzini
2024-06-08 20:14 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 24/25] target/i386: do not check PREFIX_LOCK in old-style decoder Paolo Bonzini
2024-06-08 20:15 ` Richard Henderson
2024-06-10 17:10 ` Paolo Bonzini
2024-06-08 8:41 ` [PATCH 25/25] target/i386: remove gen_ext_tl Paolo Bonzini
2024-06-08 20:17 ` Richard Henderson
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