[RFC PATCH v2 0/2] Support RISC-V CSR read/write in Qtest environment

[Ivan Klokov <ivan.klokov@syntacore.com>]

These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.

---
v2:
   - Refactor unit test, add missed files
---

Ivan Klokov (2):
  Add RISC-V CSR qtest support
  QTest example for RISC-V CSR register

 target/riscv/cpu.c             | 13 +++++++++
 target/riscv/cpu.h             |  3 +++
 target/riscv/csr.c             | 49 +++++++++++++++++++++++++++++++++-
 tests/qtest/libqos/csr.c       | 42 +++++++++++++++++++++++++++++
 tests/qtest/libqos/csr.h       | 16 +++++++++++
 tests/qtest/libqos/meson.build |  3 +++
 tests/qtest/libqtest.c         | 27 +++++++++++++++++++
 tests/qtest/libqtest.h         | 14 ++++++++++
 tests/qtest/meson.build        |  2 ++
 tests/qtest/riscv-csr-test.c   | 47 ++++++++++++++++++++++++++++++++
 10 files changed, 215 insertions(+), 1 deletion(-)
 create mode 100644 tests/qtest/libqos/csr.c
 create mode 100644 tests/qtest/libqos/csr.h
 create mode 100644 tests/qtest/riscv-csr-test.c

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2.34.1