[PATCH] docs/cxl: Fix some typos

[PATCH] docs/cxl: Fix some typos

[Davidlohr Bueso]

Found while reading the doc.

Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
---
 docs/system/devices/cxl.rst | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index abf7c1f24305..891bbd65d9d8 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -83,7 +83,7 @@ CXL Fixed Memory Windows (CFMW)
 A CFMW consists of a particular range of Host Physical Address space
 which is routed to particular CXL Host Bridges.  At time of generic
 software initialization it will have a particularly interleaving
-configuration and associated Quality of Serice Throtling Group (QTG).
+configuration and associated Quality of Service Throttling Group (QTG).
 This information is available to system software, when making
 decisions about how to configure interleave across available CXL
 memory devices.  It is provide as CFMW Structures (CFMWS) in
@@ -98,7 +98,7 @@ specification defined register interface called CXL Host Bridge
 Component Registers (CHBCR). The location of this CHBCR MMIO
 space is described to system software via a CXL Host Bridge
 Structure (CHBS) in the CEDT ACPI table.  The actual interfaces
-are identical to those used for other parts of the CXL heirarchy
+are identical to those used for other parts of the CXL hierarchy
 as CXL Component Registers in PCI BARs.
 
 Interfaces provided include:
@@ -111,7 +111,7 @@ Interfaces provided include:
 
 CXL Root Ports (CXL RP)
 ~~~~~~~~~~~~~~~~~~~~~~~
-A CXL Root Port servers te same purpose as a PCIe Root Port.
+A CXL Root Port servers the same purpose as a PCIe Root Port.
 There are a number of CXL specific Designated Vendor Specific
 Extended Capabilities (DVSEC) in PCIe Configuration Space
 and associated component register access via PCI bars.
@@ -143,7 +143,7 @@ CXL Memory Devices - Type 3
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 CXL type 3 devices use a PCI class code and are intended to be supported
 by a generic operating system driver. They have HDM decoders
-though in these EP devices, the decoder is reponsible not for
+though in these EP devices, the decoder is responsible not for
 routing but for translation of the incoming host physical address (HPA)
 into a Device Physical Address (DPA).
 
@@ -209,7 +209,7 @@ Notes:
     ranges of the system physical address map.  Each CFMW has
     particular interleave setup across the CXL Host Bridges (HB)
     CFMW0 provides uninterleaved access to HB0, CFW2 provides
-    uninterleaved acess to HB1. CFW1 provides interleaved memory access
+    uninterleaved access to HB1. CFW1 provides interleaved memory access
     across HB0 and HB1.
 
 (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
@@ -282,7 +282,7 @@ Example topology involving a switch::
             ---------------------------------------------------
            |    Switch 0  USP as PCI 0d:00.0                   |
            |    USP has HDM decoder which direct traffic to    |
-           |    appropiate downstream port                     |
+           |    appropriate downstream port                    |
            |    Switch BUS appears as 0e                       |
            |x__________________________________________________|
             |                  |               |              |
-- 
2.38.0

Re: [PATCH] docs/cxl: Fix some typos

[Ira Weiny]

On Mon, Nov 07, 2022 at 10:09:23AM -0800, Davidlohr Bueso wrote:
> Found while reading the doc.
> 
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>

Reviewed-by: Ira Weiny <ira.weiny@intel.com>

> ---
>  docs/system/devices/cxl.rst | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index abf7c1f24305..891bbd65d9d8 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -83,7 +83,7 @@ CXL Fixed Memory Windows (CFMW)
>  A CFMW consists of a particular range of Host Physical Address space
>  which is routed to particular CXL Host Bridges.  At time of generic
>  software initialization it will have a particularly interleaving
> -configuration and associated Quality of Serice Throtling Group (QTG).
> +configuration and associated Quality of Service Throttling Group (QTG).
>  This information is available to system software, when making
>  decisions about how to configure interleave across available CXL
>  memory devices.  It is provide as CFMW Structures (CFMWS) in
> @@ -98,7 +98,7 @@ specification defined register interface called CXL Host Bridge
>  Component Registers (CHBCR). The location of this CHBCR MMIO
>  space is described to system software via a CXL Host Bridge
>  Structure (CHBS) in the CEDT ACPI table.  The actual interfaces
> -are identical to those used for other parts of the CXL heirarchy
> +are identical to those used for other parts of the CXL hierarchy
>  as CXL Component Registers in PCI BARs.
>  
>  Interfaces provided include:
> @@ -111,7 +111,7 @@ Interfaces provided include:
>  
>  CXL Root Ports (CXL RP)
>  ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port servers the same purpose as a PCIe Root Port.
>  There are a number of CXL specific Designated Vendor Specific
>  Extended Capabilities (DVSEC) in PCIe Configuration Space
>  and associated component register access via PCI bars.
> @@ -143,7 +143,7 @@ CXL Memory Devices - Type 3
>  ~~~~~~~~~~~~~~~~~~~~~~~~~~~
>  CXL type 3 devices use a PCI class code and are intended to be supported
>  by a generic operating system driver. They have HDM decoders
> -though in these EP devices, the decoder is reponsible not for
> +though in these EP devices, the decoder is responsible not for
>  routing but for translation of the incoming host physical address (HPA)
>  into a Device Physical Address (DPA).
>  
> @@ -209,7 +209,7 @@ Notes:
>      ranges of the system physical address map.  Each CFMW has
>      particular interleave setup across the CXL Host Bridges (HB)
>      CFMW0 provides uninterleaved access to HB0, CFW2 provides
> -    uninterleaved acess to HB1. CFW1 provides interleaved memory access
> +    uninterleaved access to HB1. CFW1 provides interleaved memory access
>      across HB0 and HB1.
>  
>  (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
> @@ -282,7 +282,7 @@ Example topology involving a switch::
>              ---------------------------------------------------
>             |    Switch 0  USP as PCI 0d:00.0                   |
>             |    USP has HDM decoder which direct traffic to    |
> -           |    appropiate downstream port                     |
> +           |    appropriate downstream port                    |
>             |    Switch BUS appears as 0e                       |
>             |x__________________________________________________|
>              |                  |               |              |
> -- 
> 2.38.0
> 

Re: [PATCH] docs/cxl: Fix some typos

[Alison Schofield]

On Mon, Nov 07, 2022 at 10:09:23AM -0800, Davidlohr Bueso wrote:
> Found while reading the doc.
> 
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
> ---
>  docs/system/devices/cxl.rst | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index abf7c1f24305..891bbd65d9d8 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -83,7 +83,7 @@ CXL Fixed Memory Windows (CFMW)
>  A CFMW consists of a particular range of Host Physical Address space
>  which is routed to particular CXL Host Bridges.  At time of generic
to 'a' particular

>  software initialization it will have a particularly interleaving
s/particularly/particular or just remove usage of the entire word
here and above. Not sure that 'particular'  is particularly helpful
here ;)

> -configuration and associated Quality of Serice Throtling Group (QTG).
> +configuration and associated Quality of Service Throttling Group (QTG).
>  This information is available to system software, when making
>  decisions about how to configure interleave across available CXL
>  memory devices.  It is provide as CFMW Structures (CFMWS) in

s/provide/provided


> @@ -98,7 +98,7 @@ specification defined register interface called CXL Host Bridge
>  Component Registers (CHBCR). The location of this CHBCR MMIO
>  space is described to system software via a CXL Host Bridge
>  Structure (CHBS) in the CEDT ACPI table.  The actual interfaces
> -are identical to those used for other parts of the CXL heirarchy
> +are identical to those used for other parts of the CXL hierarchy
>  as CXL Component Registers in PCI BARs.
>  
>  Interfaces provided include:
> @@ -111,7 +111,7 @@ Interfaces provided include:
>  
>  CXL Root Ports (CXL RP)
>  ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port servers the same purpose as a PCIe Root Port.

s/servers/serves

>  There are a number of CXL specific Designated Vendor Specific
>  Extended Capabilities (DVSEC) in PCIe Configuration Space
>  and associated component register access via PCI bars.
> @@ -143,7 +143,7 @@ CXL Memory Devices - Type 3
>  ~~~~~~~~~~~~~~~~~~~~~~~~~~~
>  CXL type 3 devices use a PCI class code and are intended to be supported
>  by a generic operating system driver. They have HDM decoders
> -though in these EP devices, the decoder is reponsible not for
> +though in these EP devices, the decoder is responsible not for

s/"responsible not"/"not responsible"

>  routing but for translation of the incoming host physical address (HPA)
>  into a Device Physical Address (DPA).
>  
> @@ -209,7 +209,7 @@ Notes:
>      ranges of the system physical address map.  Each CFMW has
>      particular interleave setup across the CXL Host Bridges (HB)
>      CFMW0 provides uninterleaved access to HB0, CFW2 provides
> -    uninterleaved acess to HB1. CFW1 provides interleaved memory access
> +    uninterleaved access to HB1. CFW1 provides interleaved memory access
>      across HB0 and HB1.

s/CFW1/CFMW1  s/CFW2/CFMW2

>  
>  (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
> @@ -282,7 +282,7 @@ Example topology involving a switch::
>              ---------------------------------------------------
>             |    Switch 0  USP as PCI 0d:00.0                   |
>             |    USP has HDM decoder which direct traffic to    |
> -           |    appropiate downstream port                     |
> +           |    appropriate downstream port                    |

to 'the' or to 'an' approp...

>             |    Switch BUS appears as 0e                       |
>             |x__________________________________________________|
>              |                  |               |              |

OK - after picking at this a bit, and only picking at the pieces
I see in this diff, I'll suggest a check back through this section
entirely, rather than the piecemeal spelling corrections.

Alison



> -- 
> 2.38.0
> 

[PATCH] docs/cxl: fix some typos

[Hyeongtak Ji]

Signed-off-by: Hyeongtak Ji <hyeongtak.ji@gmail.com>
---
 docs/system/devices/cxl.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index 10a0e9bc9ff4..e2497e6a098b 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -218,17 +218,17 @@ Notes:
     A complex configuration here, might be to use the following HDM
     decoders in HB0. HDM0 routes CFMW0 requests to RP0 and hence
     part of CXL Type3 0. HDM1 routes CFMW0 requests from a
-    different region of the CFMW0 PA range to RP2 and hence part
+    different region of the CFMW0 PA range to RP1 and hence part
     of CXL Type 3 1.  HDM2 routes yet another PA range from within
     CFMW0 to be interleaved across RP0 and RP1, providing 2 way
     interleave of part of the memory provided by CXL Type3 0 and
     CXL Type 3 1. HDM3 routes those interleaved accesses from
     CFMW1 that target HB0 to RP 0 and another part of the memory of
     CXL Type 3 0 (as part of a 2 way interleave at the system level
-    across for example CXL Type3 0 and CXL Type3 2.
+    across for example CXL Type3 0 and CXL Type3 1).
     HDM4 is used to enable system wide 4 way interleave across all
     the present CXL type3 devices, by interleaving those (interleaved)
-    requests that HB0 receives from from CFMW1 across RP 0 and
+    requests that HB0 receives from CFMW1 across RP 0 and
     RP 1 and hence to yet more regions of the memory of the
     attached Type3 devices.  Note this is a representative subset
     of the full range of possible HDM decoder configurations in this
-- 
2.34.1

Re: [PATCH] docs/cxl: fix some typos

[Jonathan Cameron via]

On Wed, 19 Jun 2024 13:54:59 +0900
Hyeongtak Ji <hyeongtak.ji@gmail.com> wrote:

Hi, some description would be good of how you caught these
(I'm guessing a close read).

Whilst checking this I did notice there are some errors in
the example bus numbering but that's a separate issue.

Jonathan


> Signed-off-by: Hyeongtak Ji <hyeongtak.ji@gmail.com>
> ---
>  docs/system/devices/cxl.rst | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index 10a0e9bc9ff4..e2497e6a098b 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -218,17 +218,17 @@ Notes:
>      A complex configuration here, might be to use the following HDM
>      decoders in HB0. HDM0 routes CFMW0 requests to RP0 and hence
>      part of CXL Type3 0. HDM1 routes CFMW0 requests from a
> -    different region of the CFMW0 PA range to RP2 and hence part
> +    different region of the CFMW0 PA range to RP1 and hence part

Good catch.

>      of CXL Type 3 1.  HDM2 routes yet another PA range from within
>      CFMW0 to be interleaved across RP0 and RP1, providing 2 way
>      interleave of part of the memory provided by CXL Type3 0 and
>      CXL Type 3 1. HDM3 routes those interleaved accesses from
>      CFMW1 that target HB0 to RP 0 and another part of the memory of
>      CXL Type 3 0 (as part of a 2 way interleave at the system level
> -    across for example CXL Type3 0 and CXL Type3 2.
> +    across for example CXL Type3 0 and CXL Type3 1).
This one is wrong.  CFMW1 interleaves across both host bridges so we need
a device below HB0 and one below HB1, so CXL type3 2 is a possible choice
(could be CXL type3 3 as well, but that doesn't matter.)

>      HDM4 is used to enable system wide 4 way interleave across all
>      the present CXL type3 devices, by interleaving those (interleaved)
> -    requests that HB0 receives from from CFMW1 across RP 0 and
> +    requests that HB0 receives from CFMW1 across RP 0 and
Good.

>      RP 1 and hence to yet more regions of the memory of the
>      attached Type3 devices.  Note this is a representative subset
>      of the full range of possible HDM decoder configurations in this

Re: [PATCH] docs/cxl: fix some typos

[Hyeongtak Ji]

Hello Jonathan,

Thank you for your response.

On Sat, Jun 22, 2024 at 1:10 AM Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> On Wed, 19 Jun 2024 13:54:59 +0900
> Hyeongtak Ji <hyeongtak.ji@gmail.com> wrote:
>
> Hi, some description would be good of how you caught these
> (I'm guessing a close read).

Just to confirm, are you suggesting that the patch should include a
commit message?  I apologize for submitting the patch without any
sufficient explanation.  However, I am not entirely sure if "how I
found these typos" needs to be included in the commit message.  For
your information, I discovered these typos because the ASCII art did
not align with the explanations (yes, a close read).

>
> Whilst checking this I did notice there are some errors in
> the example bus numbering but that's a separate issue.
>
> Jonathan
>
>
> > Signed-off-by: Hyeongtak Ji <hyeongtak.ji@gmail.com>
> > ---
> >  docs/system/devices/cxl.rst | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> > index 10a0e9bc9ff4..e2497e6a098b 100644
> > --- a/docs/system/devices/cxl.rst
> > +++ b/docs/system/devices/cxl.rst
> > @@ -218,17 +218,17 @@ Notes:
> >      A complex configuration here, might be to use the following HDM
> >      decoders in HB0. HDM0 routes CFMW0 requests to RP0 and hence
> >      part of CXL Type3 0. HDM1 routes CFMW0 requests from a
> > -    different region of the CFMW0 PA range to RP2 and hence part
> > +    different region of the CFMW0 PA range to RP1 and hence part
>
> Good catch.
>
> >      of CXL Type 3 1.  HDM2 routes yet another PA range from within
> >      CFMW0 to be interleaved across RP0 and RP1, providing 2 way
> >      interleave of part of the memory provided by CXL Type3 0 and
> >      CXL Type 3 1. HDM3 routes those interleaved accesses from
> >      CFMW1 that target HB0 to RP 0 and another part of the memory of
> >      CXL Type 3 0 (as part of a 2 way interleave at the system level
> > -    across for example CXL Type3 0 and CXL Type3 2.
> > +    across for example CXL Type3 0 and CXL Type3 1).
> This one is wrong.  CFMW1 interleaves across both host bridges so we need
> a device below HB0 and one below HB1, so CXL type3 2 is a possible choice
> (could be CXL type3 3 as well, but that doesn't matter.)

Oh, I misunderstood the original explanation.  I will correct it just by
adding the missing parenthesis instead.

>
> >      HDM4 is used to enable system wide 4 way interleave across all
> >      the present CXL type3 devices, by interleaving those (interleaved)
> > -    requests that HB0 receives from from CFMW1 across RP 0 and
> > +    requests that HB0 receives from CFMW1 across RP 0 and
> Good.
>
> >      RP 1 and hence to yet more regions of the memory of the
> >      attached Type3 devices.  Note this is a representative subset
> >      of the full range of possible HDM decoder configurations in this
>

I will send V2 with a decent explanation and the corrected typo fix.

Kind regards,
Hyeongtak

On Sat, Jun 22, 2024 at 1:10 AM Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> On Wed, 19 Jun 2024 13:54:59 +0900
> Hyeongtak Ji <hyeongtak.ji@gmail.com> wrote:
>
> Hi, some description would be good of how you caught these
> (I'm guessing a close read).
>
> Whilst checking this I did notice there are some errors in
> the example bus numbering but that's a separate issue.
>
> Jonathan
>
>
> > Signed-off-by: Hyeongtak Ji <hyeongtak.ji@gmail.com>
> > ---
> >  docs/system/devices/cxl.rst | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> > index 10a0e9bc9ff4..e2497e6a098b 100644
> > --- a/docs/system/devices/cxl.rst
> > +++ b/docs/system/devices/cxl.rst
> > @@ -218,17 +218,17 @@ Notes:
> >      A complex configuration here, might be to use the following HDM
> >      decoders in HB0. HDM0 routes CFMW0 requests to RP0 and hence
> >      part of CXL Type3 0. HDM1 routes CFMW0 requests from a
> > -    different region of the CFMW0 PA range to RP2 and hence part
> > +    different region of the CFMW0 PA range to RP1 and hence part
>
> Good catch.
>
> >      of CXL Type 3 1.  HDM2 routes yet another PA range from within
> >      CFMW0 to be interleaved across RP0 and RP1, providing 2 way
> >      interleave of part of the memory provided by CXL Type3 0 and
> >      CXL Type 3 1. HDM3 routes those interleaved accesses from
> >      CFMW1 that target HB0 to RP 0 and another part of the memory of
> >      CXL Type 3 0 (as part of a 2 way interleave at the system level
> > -    across for example CXL Type3 0 and CXL Type3 2.
> > +    across for example CXL Type3 0 and CXL Type3 1).
> This one is wrong.  CFMW1 interleaves across both host bridges so we need
> a device below HB0 and one below HB1, so CXL type3 2 is a possible choice
> (could be CXL type3 3 as well, but that doesn't matter.)
>
> >      HDM4 is used to enable system wide 4 way interleave across all
> >      the present CXL type3 devices, by interleaving those (interleaved)
> > -    requests that HB0 receives from from CFMW1 across RP 0 and
> > +    requests that HB0 receives from CFMW1 across RP 0 and
> Good.
>
> >      RP 1 and hence to yet more regions of the memory of the
> >      attached Type3 devices.  Note this is a representative subset
> >      of the full range of possible HDM decoder configurations in this
>

Re: [PATCH] docs/cxl: fix some typos

[Jonathan Cameron via]

On Sat, 22 Jun 2024 16:25:26 +0900
Hyeongtak Ji <hyeongtak.ji@gmail.com> wrote:

> Hello Jonathan,
> 
> Thank you for your response.
> 
> On Sat, Jun 22, 2024 at 1:10 AM Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > On Wed, 19 Jun 2024 13:54:59 +0900
> > Hyeongtak Ji <hyeongtak.ji@gmail.com> wrote:
> >
> > Hi, some description would be good of how you caught these
> > (I'm guessing a close read).  
> 
> Just to confirm, are you suggesting that the patch should include a
> commit message?  I apologize for submitting the patch without any
> sufficient explanation.  However, I am not entirely sure if "how I
> found these typos" needs to be included in the commit message.  For
> your information, I discovered these typos because the ASCII art did
> not align with the explanations (yes, a close read).

Mostly just wanted a patch description that said something.
It can be useful to have even minimal info such as
"Found by inspection relative to the ASCII art above."
Helps guide if people should read closely or not!

Thanks,

Jonathan


> 
> >
> > Whilst checking this I did notice there are some errors in
> > the example bus numbering but that's a separate issue.
> >
> > Jonathan
> >
> >  
> > > Signed-off-by: Hyeongtak Ji <hyeongtak.ji@gmail.com>
> > > ---
> > >  docs/system/devices/cxl.rst | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> > > index 10a0e9bc9ff4..e2497e6a098b 100644
> > > --- a/docs/system/devices/cxl.rst
> > > +++ b/docs/system/devices/cxl.rst
> > > @@ -218,17 +218,17 @@ Notes:
> > >      A complex configuration here, might be to use the following HDM
> > >      decoders in HB0. HDM0 routes CFMW0 requests to RP0 and hence
> > >      part of CXL Type3 0. HDM1 routes CFMW0 requests from a
> > > -    different region of the CFMW0 PA range to RP2 and hence part
> > > +    different region of the CFMW0 PA range to RP1 and hence part  
> >
> > Good catch.
> >  
> > >      of CXL Type 3 1.  HDM2 routes yet another PA range from within
> > >      CFMW0 to be interleaved across RP0 and RP1, providing 2 way
> > >      interleave of part of the memory provided by CXL Type3 0 and
> > >      CXL Type 3 1. HDM3 routes those interleaved accesses from
> > >      CFMW1 that target HB0 to RP 0 and another part of the memory of
> > >      CXL Type 3 0 (as part of a 2 way interleave at the system level
> > > -    across for example CXL Type3 0 and CXL Type3 2.
> > > +    across for example CXL Type3 0 and CXL Type3 1).  
> > This one is wrong.  CFMW1 interleaves across both host bridges so we need
> > a device below HB0 and one below HB1, so CXL type3 2 is a possible choice
> > (could be CXL type3 3 as well, but that doesn't matter.)  
> 
> Oh, I misunderstood the original explanation.  I will correct it just by
> adding the missing parenthesis instead.
> 
> >  
> > >      HDM4 is used to enable system wide 4 way interleave across all
> > >      the present CXL type3 devices, by interleaving those (interleaved)
> > > -    requests that HB0 receives from from CFMW1 across RP 0 and
> > > +    requests that HB0 receives from CFMW1 across RP 0 and  
> > Good.
> >  
> > >      RP 1 and hence to yet more regions of the memory of the
> > >      attached Type3 devices.  Note this is a representative subset
> > >      of the full range of possible HDM decoder configurations in this  
> >  
> 
> I will send V2 with a decent explanation and the corrected typo fix.
> 
> Kind regards,
> Hyeongtak
> 
> On Sat, Jun 22, 2024 at 1:10 AM Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > On Wed, 19 Jun 2024 13:54:59 +0900
> > Hyeongtak Ji <hyeongtak.ji@gmail.com> wrote:
> >
> > Hi, some description would be good of how you caught these
> > (I'm guessing a close read).
> >
> > Whilst checking this I did notice there are some errors in
> > the example bus numbering but that's a separate issue.
> >
> > Jonathan
> >
> >  
> > > Signed-off-by: Hyeongtak Ji <hyeongtak.ji@gmail.com>
> > > ---
> > >  docs/system/devices/cxl.rst | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> > > index 10a0e9bc9ff4..e2497e6a098b 100644
> > > --- a/docs/system/devices/cxl.rst
> > > +++ b/docs/system/devices/cxl.rst
> > > @@ -218,17 +218,17 @@ Notes:
> > >      A complex configuration here, might be to use the following HDM
> > >      decoders in HB0. HDM0 routes CFMW0 requests to RP0 and hence
> > >      part of CXL Type3 0. HDM1 routes CFMW0 requests from a
> > > -    different region of the CFMW0 PA range to RP2 and hence part
> > > +    different region of the CFMW0 PA range to RP1 and hence part  
> >
> > Good catch.
> >  
> > >      of CXL Type 3 1.  HDM2 routes yet another PA range from within
> > >      CFMW0 to be interleaved across RP0 and RP1, providing 2 way
> > >      interleave of part of the memory provided by CXL Type3 0 and
> > >      CXL Type 3 1. HDM3 routes those interleaved accesses from
> > >      CFMW1 that target HB0 to RP 0 and another part of the memory of
> > >      CXL Type 3 0 (as part of a 2 way interleave at the system level
> > > -    across for example CXL Type3 0 and CXL Type3 2.
> > > +    across for example CXL Type3 0 and CXL Type3 1).  
> > This one is wrong.  CFMW1 interleaves across both host bridges so we need
> > a device below HB0 and one below HB1, so CXL type3 2 is a possible choice
> > (could be CXL type3 3 as well, but that doesn't matter.)
> >  
> > >      HDM4 is used to enable system wide 4 way interleave across all
> > >      the present CXL type3 devices, by interleaving those (interleaved)
> > > -    requests that HB0 receives from from CFMW1 across RP 0 and
> > > +    requests that HB0 receives from CFMW1 across RP 0 and  
> > Good.
> >  
> > >      RP 1 and hence to yet more regions of the memory of the
> > >      attached Type3 devices.  Note this is a representative subset
> > >      of the full range of possible HDM decoder configurations in this  
> >