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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6b4ff61db92sm23720096d6.30.2024.06.20.06.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 06:53:29 -0700 (PDT) Date: Thu, 20 Jun 2024 15:53:24 +0200 From: Igor Mammedov To: Sunil V L Cc: "Michael S. Tsirkin" , Philippe =?UTF-8?B?TWF0aGlldS1E?= =?UTF-8?B?YXVkw6k=?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Paolo Bonzini , =?UTF-8?B?TWFyYy1BbmRyw6k=?= Lureau , "Daniel P . =?UTF-8?B?QmVycmFuZ8Op?=" , Thomas Huth , Ani Sinha , Laurent Vivier , Gerd Hoffmann , Alistair Francis , Sia Jee Heng , Haibo1 Xu , Anup Patel , Andrew Jones , Daniel Henrique Barboza , Peter Maydell , Palmer Dabbelt , Bin Meng , Weiwei Li , Liu Zhiwei , Alistair Francis Subject: Re: [PATCH v2 06/12] tests/data/acpi/virt: Move ACPI tables under aarch64 Message-ID: <20240620155324.1d7157f9@imammedo.users.ipa.redhat.com> In-Reply-To: References: <20240524061411.341599-1-sunilvl@ventanamicro.com> <20240524061411.341599-7-sunilvl@ventanamicro.com> <27cef750-262a-402a-97fe-c4a55700a376@linaro.org> <20240619111743.58930119@imammedo.users.ipa.redhat.com> <20240619052043-mutt-send-email-mst@kernel.org> X-Mailer: Claws Mail 4.2.0 (GTK 3.24.42; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.152, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 19 Jun 2024 23:30:35 +0530 Sunil V L wrote: > On Wed, Jun 19, 2024 at 05:20:50AM -0400, Michael S. Tsirkin wrote: > > On Wed, Jun 19, 2024 at 11:17:43AM +0200, Igor Mammedov wrote: =20 > > > On Mon, 27 May 2024 20:46:29 +0530 > > > Sunil V L wrote: > > > =20 > > > > On Mon, May 27, 2024 at 12:12:10PM +0200, Philippe Mathieu-Daud=C3= =A9 wrote: =20 > > > > > Hi Sunil, > > > > >=20 > > > > > On 24/5/24 08:14, Sunil V L wrote: =20 > > > > > > Since virt is a common machine name across architectures like A= RM64 and > > > > > > RISC-V, move existing ARM64 ACPI tables under aarch64 folder so= that > > > > > > RISC-V tables can be added under riscv64 folder in future. > > > > > >=20 > > > > > > Signed-off-by: Sunil V L > > > > > > Reviewed-by: Alistair Francis > > > > > > --- > > > > > > tests/data/acpi/virt/{ =3D> aarch64}/APIC | Bin = =20 > > > > >=20 > > > > > The usual pattern is {target}/{machine}, so instead of: > > > > >=20 > > > > > microvm/ > > > > > pc/ > > > > > q35/ > > > > > virt/aarch64/ > > > > > virt/riscv64/ > > > > >=20 > > > > > (which is odd because q35 is the x86 'virt'), I'd rather see: > > > > >=20 > > > > > x86/microvm/ > > > > > x86/pc/ > > > > > x86/q35/ > > > > > aarch64/virt/ > > > > > riscv64/virt/ > > > > >=20 > > > > > Anyhow just my 2 cents, up to the ACPI maintainers :) > > > > > =20 > > > > Hi Phil, > > > >=20 > > > > Your suggestion does make sense to me. Let me wait for feedback from > > > > ARM/ACPI maintainers. =20 > > >=20 > > > I'd prefer {target}/{machine} hierarchy like Philippe suggests =20 > >=20 > > Agreed. > > =20 > Thanks for the confirmation!. Let me send the updated version soon. >=20 > Moving pc/q35/microvm also under new x86 would need many changes in > bios-table-test.c. So, the question is, are you ok to combine x86 > changes as well in this series or prefer to it later in separate series? it should be fine ok to include x86 changes here as well. I'd basically split previous patch on path altering part and a 2nd adding .arch =3D "aarch64" then 3rd doing the same for x86 as for this patch, I'd include all blobs movement here. >=20 > Thanks, > Sunil >=20