From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-stable@nongnu.org
Subject: [PATCH 01/13] target/arm: Fix VCMLA Dd, Dn, Dm[idx]
Date: Mon, 24 Jun 2024 22:07:58 -0700 [thread overview]
Message-ID: <20240625050810.1475643-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240625050810.1475643-1-richard.henderson@linaro.org>
The inner loop, bounded by eltspersegment, must not be
larger than the outer loop, bounded by elements.
Cc: qemu-stable@nongnu.org
Fixes: 18fc2405781 ("target/arm: Implement SVE fp complex multiply add (indexed)")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2376
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/vec_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index b05922b425..7b34cc98af 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -907,7 +907,7 @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
uint32_t neg_real = flip ^ neg_imag;
intptr_t elements = opr_sz / sizeof(float16);
- intptr_t eltspersegment = 16 / sizeof(float16);
+ intptr_t eltspersegment = MIN(16 / sizeof(float16), elements);
intptr_t i, j;
/* Shift boolean to the sign bit so we can xor to negate. */
@@ -969,7 +969,7 @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
uint32_t neg_real = flip ^ neg_imag;
intptr_t elements = opr_sz / sizeof(float32);
- intptr_t eltspersegment = 16 / sizeof(float32);
+ intptr_t eltspersegment = MIN(16 / sizeof(float32), elements);
intptr_t i, j;
/* Shift boolean to the sign bit so we can xor to negate. */
--
2.34.1
next prev parent reply other threads:[~2024-06-25 5:09 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-25 5:07 [PATCH 00/13] target/arm: AdvSIMD conversion, part 2 Richard Henderson
2024-06-25 5:07 ` Richard Henderson [this message]
2024-06-25 11:42 ` [PATCH 01/13] target/arm: Fix VCMLA Dd, Dn, Dm[idx] Peter Maydell
2024-06-25 5:07 ` [PATCH 02/13] target/arm: Fix SQDMULH (by element) with Q=0 Richard Henderson
2024-06-25 11:43 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 03/13] target/arm: Fix FJCVTZS vs flush-to-zero Richard Henderson
2024-06-25 11:56 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 04/13] target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree Richard Henderson
2024-06-25 12:38 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 05/13] target/arm: Convert SDOT, UDOT " Richard Henderson
2024-06-25 12:38 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 06/13] target/arm: Convert SUDOT, USDOT " Richard Henderson
2024-06-25 12:37 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 07/13] target/arm: Convert BFDOT " Richard Henderson
2024-06-25 12:42 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 08/13] target/arm: Convert BFMLALB, BFMLALT " Richard Henderson
2024-06-25 12:38 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 09/13] target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA " Richard Henderson
2024-06-25 12:42 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 10/13] target/arm: Add data argument to do_fp3_vector Richard Henderson
2024-06-25 12:43 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 11/13] target/arm: Convert FCADD to decodetree Richard Henderson
2024-06-25 12:41 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 12/13] target/arm: Convert FCMLA " Richard Henderson
2024-06-25 12:35 ` Peter Maydell
2024-06-25 5:08 ` [PATCH 13/13] target/arm: Delete dead code from disas_simd_indexed Richard Henderson
2024-06-25 12:41 ` Peter Maydell
2024-06-25 14:18 ` Richard Henderson
2024-06-25 14:21 ` Peter Maydell
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