From: Akihiko Odaki <akihiko.odaki@daynix.com>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Akihiko Odaki <akihiko.odaki@daynix.com>
Subject: [PATCH v2 2/6] tests/tcg/aarch64: Fix test architecture specification
Date: Thu, 27 Jun 2024 22:58:03 +0900 [thread overview]
Message-ID: <20240627-tcg-v2-2-1690a813348e@daynix.com> (raw)
In-Reply-To: <20240627-tcg-v2-0-1690a813348e@daynix.com>
sme-smopa-2.c requires sme-i16i64 but the compiler option used not to
specify it. Instead, the extension was specified with the inline
assembly, resulting in mixing assembly code targeting sme-i1664 and C
code that does not target sme-i1664.
clang version 18.1.6 does not support such mixing so properly specify
the extension with the compiler option instead.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
tests/tcg/aarch64/sme-smopa-2.c | 2 +-
tests/tcg/aarch64/Makefile.target | 11 +++++++++--
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c
index c9f48c3bfca2..2c9707065992 100644
--- a/tests/tcg/aarch64/sme-smopa-2.c
+++ b/tests/tcg/aarch64/sme-smopa-2.c
@@ -14,7 +14,7 @@ int main()
long svl;
/* Validate that we have a wide enough vector for 4 elements. */
- asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
+ asm("rdsvl %0, #1" : "=r"(svl));
if (svl < 32) {
return 0;
}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 70d728ae9af7..ad99e0e3b198 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -27,7 +27,8 @@ config-cc.mak: Makefile
$(call cc-option,-march=armv8.5-a, CROSS_CC_HAS_ARMV8_5); \
$(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
$(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
- $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak
+ $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME); \
+ $(call cc-option,-march=armv9-a+sme-i16i64, CROSS_AS_HAS_ARMV9_SME_I1664)) 3> config-cc.mak
-include config-cc.mak
ifneq ($(CROSS_CC_HAS_ARMV8_2),)
@@ -68,7 +69,13 @@ endif
# SME Tests
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
-AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
+AARCH64_TESTS += sme-outprod1 sme-smopa-1
+endif
+
+# SME I16I64 Tests
+ifneq ($(CROSS_AS_HAS_ARMV9_SME_I1664),)
+AARCH64_TESTS += sme-smopa-2
+sme-smopa-2: CFLAGS += -march=armv9-a+sme-i16i64
endif
# System Registers Tests
--
2.45.2
next prev parent reply other threads:[~2024-06-27 13:59 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-27 13:58 [PATCH v2 0/6] tests/tcg/aarch64: Fix inline assemblies for clang Akihiko Odaki
2024-06-27 13:58 ` [PATCH v2 1/6] tests/tcg/arm: Fix fcvt result messages Akihiko Odaki
2024-06-28 12:33 ` Alex Bennée
2024-06-28 17:11 ` Richard Henderson
2024-06-27 13:58 ` Akihiko Odaki [this message]
2024-06-28 17:18 ` [PATCH v2 2/6] tests/tcg/aarch64: Fix test architecture specification Richard Henderson
2024-06-27 13:58 ` [PATCH v2 3/6] tests/tcg/aarch64: Explicitly specify register width Akihiko Odaki
2024-06-28 17:19 ` Richard Henderson
2024-06-29 8:54 ` Akihiko Odaki
2024-06-27 13:58 ` [PATCH v2 4/6] tests/tcg/aarch64: Fix irg operand type Akihiko Odaki
2024-06-28 17:19 ` Richard Henderson
2024-06-27 13:58 ` [PATCH v2 5/6] tests/tcg/aarch64: Do not use x constraint Akihiko Odaki
2024-06-28 17:20 ` Richard Henderson
2024-06-27 13:58 ` [PATCH v2 6/6] tests/tcg/arm: Manually bit-cast half-precision numbers Akihiko Odaki
2024-06-28 12:30 ` [PATCH v2 0/6] tests/tcg/aarch64: Fix inline assemblies for clang Alex Bennée
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