From: Akihiko Odaki <akihiko.odaki@daynix.com>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Akihiko Odaki <akihiko.odaki@daynix.com>
Subject: [PATCH v2 3/6] tests/tcg/aarch64: Explicitly specify register width
Date: Thu, 27 Jun 2024 22:58:04 +0900 [thread overview]
Message-ID: <20240627-tcg-v2-3-1690a813348e@daynix.com> (raw)
In-Reply-To: <20240627-tcg-v2-0-1690a813348e@daynix.com>
clang version 18.1.6 assumes a register is 64-bit by default and
complains if a 32-bit value is given. Explicitly specify register width
when passing a 32-bit value.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
tests/tcg/aarch64/bti-1.c | 6 +++---
tests/tcg/aarch64/bti-3.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c
index 99a879af23d4..1fada8108d22 100644
--- a/tests/tcg/aarch64/bti-1.c
+++ b/tests/tcg/aarch64/bti-1.c
@@ -17,15 +17,15 @@ static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
#define BTI_JC "hint #38"
#define BTYPE_1(DEST) \
- asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \
+ asm("mov %w0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %w0,#0" \
: "=r"(skipped) : : "x16")
#define BTYPE_2(DEST) \
- asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \
+ asm("mov %w0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %w0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_3(DEST) \
- asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \
+ asm("mov %w0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %w0,#0" \
: "=r"(skipped) : : "x15")
#define TEST(WHICH, DEST, EXPECT) \
diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
index 8c534c09d784..6a3bd037bcd6 100644
--- a/tests/tcg/aarch64/bti-3.c
+++ b/tests/tcg/aarch64/bti-3.c
@@ -11,15 +11,15 @@ static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
}
#define BTYPE_1() \
- asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
+ asm("mov %w0,#1; adr x16, 1f; br x16; 1: hint #25; mov %w0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_2() \
- asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
+ asm("mov %w0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %w0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_3() \
- asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
+ asm("mov %w0,#1; adr x15, 1f; br x15; 1: hint #25; mov %w0,#0" \
: "=r"(skipped) : : "x15", "x30")
#define TEST(WHICH, EXPECT) \
--
2.45.2
next prev parent reply other threads:[~2024-06-27 13:59 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-27 13:58 [PATCH v2 0/6] tests/tcg/aarch64: Fix inline assemblies for clang Akihiko Odaki
2024-06-27 13:58 ` [PATCH v2 1/6] tests/tcg/arm: Fix fcvt result messages Akihiko Odaki
2024-06-28 12:33 ` Alex Bennée
2024-06-28 17:11 ` Richard Henderson
2024-06-27 13:58 ` [PATCH v2 2/6] tests/tcg/aarch64: Fix test architecture specification Akihiko Odaki
2024-06-28 17:18 ` Richard Henderson
2024-06-27 13:58 ` Akihiko Odaki [this message]
2024-06-28 17:19 ` [PATCH v2 3/6] tests/tcg/aarch64: Explicitly specify register width Richard Henderson
2024-06-29 8:54 ` Akihiko Odaki
2024-06-27 13:58 ` [PATCH v2 4/6] tests/tcg/aarch64: Fix irg operand type Akihiko Odaki
2024-06-28 17:19 ` Richard Henderson
2024-06-27 13:58 ` [PATCH v2 5/6] tests/tcg/aarch64: Do not use x constraint Akihiko Odaki
2024-06-28 17:20 ` Richard Henderson
2024-06-27 13:58 ` [PATCH v2 6/6] tests/tcg/arm: Manually bit-cast half-precision numbers Akihiko Odaki
2024-06-28 12:30 ` [PATCH v2 0/6] tests/tcg/aarch64: Fix inline assemblies for clang Alex Bennée
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