* [PATCH 1/3] target/riscv: zimop and zcmop extension for riscv
@ 2024-06-28 17:50 Deepak Gupta
2024-06-28 18:03 ` Deepak Gupta
0 siblings, 1 reply; 5+ messages in thread
From: Deepak Gupta @ 2024-06-28 17:50 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Deepak Gupta, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei
`zimop` stands for `may be operations`. `zcmop` stands for compressed
`may be operations`. For some RISC-V CPU extension, once compiled into
the binary are part of generated code which can't be gated behind a probe
of whether an instruction set is supported or not. One such example is
`zicfiss` [1] extension where `shadow stack push` and `shadow stack pop
and check` will be part of every function body. Thus binaries compiled
with such extensions need to run in following scenarios
- On machines where extension is present and enabled
- On machines where extension is present and disabled
- On machines where extension is not present/implemented.
`zimop` (for 32bit instructions) and `zcmop` (for compressed) were devised
and defined [2] to support such future (like zicfiss) CPU extensions
where zimops and zcmops provide a base non-faulting behavior for
codepoints that may claimed by future ISA extensions. Minimally, any
CPU implementation wanting to have binary compatibility with such
binaries only has to implement `zimop and zcmop`. Furthermore, this
allows per-task optin for software where user has the option to enable
the feature on per-task basis.
`zimop` are defined to write zero to `rd`. `zcmop` are defined to *not* write
to any register.
[1] - https://github.com/riscv/riscv-cfi/blob/main/src/cfi_backward.adoc
[2] - https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eb1a2e7d6d..3caf8553d1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -113,6 +113,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
+ ISA_EXT_DATA_ENTRY(zimops, PRIV_VERSION_1_12_0, ext_zimops),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
@@ -2273,6 +2274,7 @@ static Property riscv_cpu_properties[] = {
* it with -x and default to 'false'.
*/
DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
+ DEFINE_PROP_BOOL("zimops", RISCVCPU, cfg.ext_zimops, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index cb750154bd..5c42ff8cdf 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -124,6 +124,7 @@ struct RISCVCPUConfig {
uint32_t mvendorid;
uint64_t marchid;
uint64_t mimpid;
+ bool ext_zimops;
/* Named features */
bool ext_svade;
--
2.34.1
From 4d15b0e0037f444eb75e60b398e19dcf476f07d4 Mon Sep 17 00:00:00 2001
From: Deepak Gupta <debug@rivosinc.com>
Date: Fri, 28 Jun 2024 00:13:58 -0700
Subject: [PATCH 2/3] target/riscv: zimop instruction encoding and its
implementation
This patch adds assigned codepoints for decoder for 32bit instructions
and provide implementation for instruction. If extension is present,
then moves 0 to `rd`.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
target/riscv/insn32.decode | 15 +++++++
target/riscv/insn_trans/trans_zimops.c.inc | 50 ++++++++++++++++++++++
target/riscv/translate.c | 3 ++
3 files changed, 68 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_zimops.c.inc
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f22df04cfd..fca3838a9f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -167,6 +167,21 @@ csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
+# zimops (unpriv integer may be operations) instructions with system opcode
+# zimops_r and zimops_rr are two code points assigned to zimops
+# Any new extension that claims zimops encoding should be placed above mop.r
+# and mop.rr
+
+# mop.r
+{
+ zimops_r 1-00--0 111-- ----- 100 ..... 1110011 %rd
+}
+
+# mop.rr
+{
+ zimops_rr 1-00--1 ----- ----- 100 ..... 1110011 %rd
+}
+
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
ld ............ ..... 011 ..... 0000011 @i
diff --git a/target/riscv/insn_trans/trans_zimops.c.inc b/target/riscv/insn_trans/trans_zimops.c.inc
new file mode 100644
index 0000000000..b5ad7bded8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_zimops.c.inc
@@ -0,0 +1,50 @@
+/*
+ * RISC-V translation routines for the Control-Flow Integrity Extension
+ *
+ * Copyright (c) 2024 Rivos Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+static bool trans_zimops_r(DisasContext *ctx, arg_zimops_r * a)
+{
+ /* zimops not implemented, raise illegal instruction & return true */
+ if (!ctx->cfg_ptr->ext_zimops) {
+ gen_exception_illegal(ctx);
+ return true;
+ }
+ /*
+ * zimops implemented, simply grab destination and mov zero.
+ * return true
+ */
+ TCGv dest = dest_gpr(ctx, a->rd);
+ dest = tcg_constant_tl(0);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_zimops_rr(DisasContext *ctx, arg_zimops_r * a)
+{
+ /* zimops not implemented, raise illegal instruction & return true */
+ if (!ctx->cfg_ptr->ext_zimops) {
+ gen_exception_illegal(ctx);
+ return true;
+ }
+ /*
+ * zimops implemented, simply grab destination and mov zero.
+ * return true
+ */
+ TCGv dest = dest_gpr(ctx, a->rd);
+ dest = tcg_constant_tl(0);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2c27fd4ce1..b7fd3456c8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1115,6 +1115,9 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
/* Include decoders for factored-out extensions */
#include "decode-XVentanaCondOps.c.inc"
+/* Include decoder for zimop */
+#include "insn_trans/trans_zimops.c.inc"
+
/* The specification allows for longer insns, but not supported by qemu. */
#define MAX_INSN_LEN 4
--
2.34.1
From dc5d2c62475ac7a9cf42b9ed1398961505b8b91d Mon Sep 17 00:00:00 2001
From: Deepak Gupta <debug@rivosinc.com>
Date: Tue, 2 Jan 2024 15:46:13 -0800
Subject: [PATCH 3/3] target/riscv: Introduce `compressed zimop` aka `zcmop`
Analogous to zimop, there are 8 encodings carved out of illegal space
encodings (c.lui xn, 0) in compressed instructions which are defined
to be zcmops short for compressed may be operations.
Unlike zimops (which write 0 to rd), zcmops don't actually write anything
to any register. Their encodings allow future extensions to define them to
read register x[n].
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
target/riscv/insn16.decode | 6 ++++++
target/riscv/insn_trans/trans_zimops.c.inc | 11 +++++++++++
2 files changed, 17 insertions(+)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index b96c534e73..d24b54d319 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -32,6 +32,7 @@
%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
+%zcmop_n 8:3
%shlimm_6bit 12:1 2:5 !function=ex_rvc_shiftli
%shrimm_6bit 12:1 2:5 !function=ex_rvc_shiftri
@@ -66,6 +67,8 @@
&cmpp urlist spimm
&cmjt index
+&cmop zcmop_n
+
# Formats 16:
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
@@ -109,6 +112,8 @@
@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
@cm_jt ... ... ........ .. &cmjt %index
+@c_mop ... . ..... ..... .. &cmop %zcmop_n
+
# *** RV32/64C Standard Extension (Quadrant 0) ***
{
# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
@@ -140,6 +145,7 @@ sw 110 ... ... .. ... 00 @cs_w
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
{
+ zcmops 011 0 0...1 00000 01 @c_mop # zcmop carving out of illegal c.lui xn,0 space
illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
addi 011 . 00010 ..... 01 @c_addi16sp
lui 011 . ..... ..... 01 @c_lui
diff --git a/target/riscv/insn_trans/trans_zimops.c.inc b/target/riscv/insn_trans/trans_zimops.c.inc
index b5ad7bded8..99f25bd9ea 100644
--- a/target/riscv/insn_trans/trans_zimops.c.inc
+++ b/target/riscv/insn_trans/trans_zimops.c.inc
@@ -48,3 +48,14 @@ static bool trans_zimops_rr(DisasContext *ctx, arg_zimops_r * a)
gen_set_gpr(ctx, a->rd, dest);
return true;
}
+
+static bool trans_zcmops(DisasContext *ctx, arg_zcmops * a)
+{
+ /* zimops not implemented, return false */
+ if (!ctx->cfg_ptr->ext_zimops) {
+ gen_exception_illegal(ctx);
+ return false;
+ }
+
+ return true;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 1/3] target/riscv: zimop and zcmop extension for riscv
@ 2024-06-28 18:01 Deepak Gupta
2024-06-28 18:01 ` [PATCH 2/3] target/riscv: zimop instruction encoding and its implementation Deepak Gupta
2024-06-28 18:01 ` [PATCH 3/3] target/riscv: Introduce `compressed zimop` aka `zcmop` Deepak Gupta
0 siblings, 2 replies; 5+ messages in thread
From: Deepak Gupta @ 2024-06-28 18:01 UTC (permalink / raw)
To: qemu-devel
Cc: Deepak Gupta, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
open list:RISC-V TCG CPUs
`zimop` stands for `may be operations`. `zcmop` stands for compressed
`may be operations`. For some RISC-V CPU extension, once compiled into
the binary are part of generated code which can't be gated behind a probe
of whether an instruction set is supported or not. One such example is
`zicfiss` [1] extension where `shadow stack push` and `shadow stack pop
and check` will be part of every function body. Thus binaries compiled
with such extensions need to run in following scenarios
- On machines where extension is present and enabled
- On machines where extension is present and disabled
- On machines where extension is not present/implemented.
`zimop` (for 32bit instructions) and `zcmop` (for compressed) were devised
and defined [2] to support such future (like zicfiss) CPU extensions
where zimops and zcmops provide a base non-faulting behavior for
codepoints that may claimed by future ISA extensions. Minimally, any
CPU implementation wanting to have binary compatibility with such
binaries only has to implement `zimop and zcmop`. Furthermore, this
allows per-task optin for software where user has the option to enable
the feature on per-task basis.
`zimop` are defined to write zero to `rd`. `zcmop` are defined to *not* write
to any register.
[1] - https://github.com/riscv/riscv-cfi/blob/main/src/cfi_backward.adoc
[2] - https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eb1a2e7d6d..3caf8553d1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -113,6 +113,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
+ ISA_EXT_DATA_ENTRY(zimops, PRIV_VERSION_1_12_0, ext_zimops),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
@@ -2273,6 +2274,7 @@ static Property riscv_cpu_properties[] = {
* it with -x and default to 'false'.
*/
DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
+ DEFINE_PROP_BOOL("zimops", RISCVCPU, cfg.ext_zimops, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index cb750154bd..5c42ff8cdf 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -124,6 +124,7 @@ struct RISCVCPUConfig {
uint32_t mvendorid;
uint64_t marchid;
uint64_t mimpid;
+ bool ext_zimops;
/* Named features */
bool ext_svade;
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/3] target/riscv: zimop instruction encoding and its implementation
2024-06-28 18:01 [PATCH 1/3] target/riscv: zimop and zcmop extension for riscv Deepak Gupta
@ 2024-06-28 18:01 ` Deepak Gupta
2024-06-28 18:01 ` [PATCH 3/3] target/riscv: Introduce `compressed zimop` aka `zcmop` Deepak Gupta
1 sibling, 0 replies; 5+ messages in thread
From: Deepak Gupta @ 2024-06-28 18:01 UTC (permalink / raw)
To: qemu-devel
Cc: Deepak Gupta, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
open list:RISC-V TCG CPUs
This patch adds assigned codepoints for decoder for 32bit instructions
and provide implementation for instruction. If extension is present,
then moves 0 to `rd`.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
target/riscv/insn32.decode | 15 +++++++
target/riscv/insn_trans/trans_zimops.c.inc | 50 ++++++++++++++++++++++
target/riscv/translate.c | 3 ++
3 files changed, 68 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_zimops.c.inc
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f22df04cfd..fca3838a9f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -167,6 +167,21 @@ csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
+# zimops (unpriv integer may be operations) instructions with system opcode
+# zimops_r and zimops_rr are two code points assigned to zimops
+# Any new extension that claims zimops encoding should be placed above mop.r
+# and mop.rr
+
+# mop.r
+{
+ zimops_r 1-00--0 111-- ----- 100 ..... 1110011 %rd
+}
+
+# mop.rr
+{
+ zimops_rr 1-00--1 ----- ----- 100 ..... 1110011 %rd
+}
+
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
ld ............ ..... 011 ..... 0000011 @i
diff --git a/target/riscv/insn_trans/trans_zimops.c.inc b/target/riscv/insn_trans/trans_zimops.c.inc
new file mode 100644
index 0000000000..b5ad7bded8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_zimops.c.inc
@@ -0,0 +1,50 @@
+/*
+ * RISC-V translation routines for the Control-Flow Integrity Extension
+ *
+ * Copyright (c) 2024 Rivos Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+static bool trans_zimops_r(DisasContext *ctx, arg_zimops_r * a)
+{
+ /* zimops not implemented, raise illegal instruction & return true */
+ if (!ctx->cfg_ptr->ext_zimops) {
+ gen_exception_illegal(ctx);
+ return true;
+ }
+ /*
+ * zimops implemented, simply grab destination and mov zero.
+ * return true
+ */
+ TCGv dest = dest_gpr(ctx, a->rd);
+ dest = tcg_constant_tl(0);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_zimops_rr(DisasContext *ctx, arg_zimops_r * a)
+{
+ /* zimops not implemented, raise illegal instruction & return true */
+ if (!ctx->cfg_ptr->ext_zimops) {
+ gen_exception_illegal(ctx);
+ return true;
+ }
+ /*
+ * zimops implemented, simply grab destination and mov zero.
+ * return true
+ */
+ TCGv dest = dest_gpr(ctx, a->rd);
+ dest = tcg_constant_tl(0);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2c27fd4ce1..b7fd3456c8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1115,6 +1115,9 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
/* Include decoders for factored-out extensions */
#include "decode-XVentanaCondOps.c.inc"
+/* Include decoder for zimop */
+#include "insn_trans/trans_zimops.c.inc"
+
/* The specification allows for longer insns, but not supported by qemu. */
#define MAX_INSN_LEN 4
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/3] target/riscv: Introduce `compressed zimop` aka `zcmop`
2024-06-28 18:01 [PATCH 1/3] target/riscv: zimop and zcmop extension for riscv Deepak Gupta
2024-06-28 18:01 ` [PATCH 2/3] target/riscv: zimop instruction encoding and its implementation Deepak Gupta
@ 2024-06-28 18:01 ` Deepak Gupta
1 sibling, 0 replies; 5+ messages in thread
From: Deepak Gupta @ 2024-06-28 18:01 UTC (permalink / raw)
To: qemu-devel
Cc: Deepak Gupta, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
open list:RISC-V TCG CPUs
Analogous to zimop, there are 8 encodings carved out of illegal space
encodings (c.lui xn, 0) in compressed instructions which are defined
to be zcmops short for compressed may be operations.
Unlike zimops (which write 0 to rd), zcmops don't actually write anything
to any register. Their encodings allow future extensions to define them to
read register x[n].
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
target/riscv/insn16.decode | 6 ++++++
target/riscv/insn_trans/trans_zimops.c.inc | 11 +++++++++++
2 files changed, 17 insertions(+)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index b96c534e73..d24b54d319 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -32,6 +32,7 @@
%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
+%zcmop_n 8:3
%shlimm_6bit 12:1 2:5 !function=ex_rvc_shiftli
%shrimm_6bit 12:1 2:5 !function=ex_rvc_shiftri
@@ -66,6 +67,8 @@
&cmpp urlist spimm
&cmjt index
+&cmop zcmop_n
+
# Formats 16:
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
@@ -109,6 +112,8 @@
@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
@cm_jt ... ... ........ .. &cmjt %index
+@c_mop ... . ..... ..... .. &cmop %zcmop_n
+
# *** RV32/64C Standard Extension (Quadrant 0) ***
{
# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
@@ -140,6 +145,7 @@ sw 110 ... ... .. ... 00 @cs_w
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
{
+ zcmops 011 0 0...1 00000 01 @c_mop # zcmop carving out of illegal c.lui xn,0 space
illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
addi 011 . 00010 ..... 01 @c_addi16sp
lui 011 . ..... ..... 01 @c_lui
diff --git a/target/riscv/insn_trans/trans_zimops.c.inc b/target/riscv/insn_trans/trans_zimops.c.inc
index b5ad7bded8..99f25bd9ea 100644
--- a/target/riscv/insn_trans/trans_zimops.c.inc
+++ b/target/riscv/insn_trans/trans_zimops.c.inc
@@ -48,3 +48,14 @@ static bool trans_zimops_rr(DisasContext *ctx, arg_zimops_r * a)
gen_set_gpr(ctx, a->rd, dest);
return true;
}
+
+static bool trans_zcmops(DisasContext *ctx, arg_zcmops * a)
+{
+ /* zimops not implemented, return false */
+ if (!ctx->cfg_ptr->ext_zimops) {
+ gen_exception_illegal(ctx);
+ return false;
+ }
+
+ return true;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] target/riscv: zimop and zcmop extension for riscv
2024-06-28 17:50 [PATCH 1/3] target/riscv: zimop and zcmop extension for riscv Deepak Gupta
@ 2024-06-28 18:03 ` Deepak Gupta
0 siblings, 0 replies; 5+ messages in thread
From: Deepak Gupta @ 2024-06-28 18:03 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
Please ignore this one.
Wrong command and all patches came out as one.
Sorry about that.
On Fri, Jun 28, 2024 at 10:50 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> `zimop` stands for `may be operations`. `zcmop` stands for compressed
> `may be operations`. For some RISC-V CPU extension, once compiled into
> the binary are part of generated code which can't be gated behind a probe
> of whether an instruction set is supported or not. One such example is
> `zicfiss` [1] extension where `shadow stack push` and `shadow stack pop
> and check` will be part of every function body. Thus binaries compiled
> with such extensions need to run in following scenarios
>
> - On machines where extension is present and enabled
> - On machines where extension is present and disabled
> - On machines where extension is not present/implemented.
>
> `zimop` (for 32bit instructions) and `zcmop` (for compressed) were devised
> and defined [2] to support such future (like zicfiss) CPU extensions
> where zimops and zcmops provide a base non-faulting behavior for
> codepoints that may claimed by future ISA extensions. Minimally, any
> CPU implementation wanting to have binary compatibility with such
> binaries only has to implement `zimop and zcmop`. Furthermore, this
> allows per-task optin for software where user has the option to enable
> the feature on per-task basis.
>
> `zimop` are defined to write zero to `rd`. `zcmop` are defined to *not* write
> to any register.
>
> [1] - https://github.com/riscv/riscv-cfi/blob/main/src/cfi_backward.adoc
> [2] - https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu_cfg.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eb1a2e7d6d..3caf8553d1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -113,6 +113,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
> ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
> ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
> + ISA_EXT_DATA_ENTRY(zimops, PRIV_VERSION_1_12_0, ext_zimops),
> ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
> ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11),
> ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
> @@ -2273,6 +2274,7 @@ static Property riscv_cpu_properties[] = {
> * it with -x and default to 'false'.
> */
> DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
> + DEFINE_PROP_BOOL("zimops", RISCVCPU, cfg.ext_zimops, true),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index cb750154bd..5c42ff8cdf 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -124,6 +124,7 @@ struct RISCVCPUConfig {
> uint32_t mvendorid;
> uint64_t marchid;
> uint64_t mimpid;
> + bool ext_zimops;
>
> /* Named features */
> bool ext_svade;
> --
> 2.34.1
>
>
> From 4d15b0e0037f444eb75e60b398e19dcf476f07d4 Mon Sep 17 00:00:00 2001
> From: Deepak Gupta <debug@rivosinc.com>
> Date: Fri, 28 Jun 2024 00:13:58 -0700
> Subject: [PATCH 2/3] target/riscv: zimop instruction encoding and its
> implementation
>
> This patch adds assigned codepoints for decoder for 32bit instructions
> and provide implementation for instruction. If extension is present,
> then moves 0 to `rd`.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---
> target/riscv/insn32.decode | 15 +++++++
> target/riscv/insn_trans/trans_zimops.c.inc | 50 ++++++++++++++++++++++
> target/riscv/translate.c | 3 ++
> 3 files changed, 68 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_zimops.c.inc
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index f22df04cfd..fca3838a9f 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -167,6 +167,21 @@ csrrwi ............ ..... 101 ..... 1110011 @csr
> csrrsi ............ ..... 110 ..... 1110011 @csr
> csrrci ............ ..... 111 ..... 1110011 @csr
>
> +# zimops (unpriv integer may be operations) instructions with system opcode
> +# zimops_r and zimops_rr are two code points assigned to zimops
> +# Any new extension that claims zimops encoding should be placed above mop.r
> +# and mop.rr
> +
> +# mop.r
> +{
> + zimops_r 1-00--0 111-- ----- 100 ..... 1110011 %rd
> +}
> +
> +# mop.rr
> +{
> + zimops_rr 1-00--1 ----- ----- 100 ..... 1110011 %rd
> +}
> +
> # *** RV64I Base Instruction Set (in addition to RV32I) ***
> lwu ............ ..... 110 ..... 0000011 @i
> ld ............ ..... 011 ..... 0000011 @i
> diff --git a/target/riscv/insn_trans/trans_zimops.c.inc b/target/riscv/insn_trans/trans_zimops.c.inc
> new file mode 100644
> index 0000000000..b5ad7bded8
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_zimops.c.inc
> @@ -0,0 +1,50 @@
> +/*
> + * RISC-V translation routines for the Control-Flow Integrity Extension
> + *
> + * Copyright (c) 2024 Rivos Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +static bool trans_zimops_r(DisasContext *ctx, arg_zimops_r * a)
> +{
> + /* zimops not implemented, raise illegal instruction & return true */
> + if (!ctx->cfg_ptr->ext_zimops) {
> + gen_exception_illegal(ctx);
> + return true;
> + }
> + /*
> + * zimops implemented, simply grab destination and mov zero.
> + * return true
> + */
> + TCGv dest = dest_gpr(ctx, a->rd);
> + dest = tcg_constant_tl(0);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +static bool trans_zimops_rr(DisasContext *ctx, arg_zimops_r * a)
> +{
> + /* zimops not implemented, raise illegal instruction & return true */
> + if (!ctx->cfg_ptr->ext_zimops) {
> + gen_exception_illegal(ctx);
> + return true;
> + }
> + /*
> + * zimops implemented, simply grab destination and mov zero.
> + * return true
> + */
> + TCGv dest = dest_gpr(ctx, a->rd);
> + dest = tcg_constant_tl(0);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2c27fd4ce1..b7fd3456c8 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1115,6 +1115,9 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> /* Include decoders for factored-out extensions */
> #include "decode-XVentanaCondOps.c.inc"
>
> +/* Include decoder for zimop */
> +#include "insn_trans/trans_zimops.c.inc"
> +
> /* The specification allows for longer insns, but not supported by qemu. */
> #define MAX_INSN_LEN 4
>
> --
> 2.34.1
>
>
> From dc5d2c62475ac7a9cf42b9ed1398961505b8b91d Mon Sep 17 00:00:00 2001
> From: Deepak Gupta <debug@rivosinc.com>
> Date: Tue, 2 Jan 2024 15:46:13 -0800
> Subject: [PATCH 3/3] target/riscv: Introduce `compressed zimop` aka `zcmop`
>
> Analogous to zimop, there are 8 encodings carved out of illegal space
> encodings (c.lui xn, 0) in compressed instructions which are defined
> to be zcmops short for compressed may be operations.
>
> Unlike zimops (which write 0 to rd), zcmops don't actually write anything
> to any register. Their encodings allow future extensions to define them to
> read register x[n].
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---
> target/riscv/insn16.decode | 6 ++++++
> target/riscv/insn_trans/trans_zimops.c.inc | 11 +++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index b96c534e73..d24b54d319 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -32,6 +32,7 @@
> %uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
> %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
> %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
> +%zcmop_n 8:3
>
> %shlimm_6bit 12:1 2:5 !function=ex_rvc_shiftli
> %shrimm_6bit 12:1 2:5 !function=ex_rvc_shiftri
> @@ -66,6 +67,8 @@
> &cmpp urlist spimm
> &cmjt index
>
> +&cmop zcmop_n
> +
> # Formats 16:
> @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
> @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
> @@ -109,6 +112,8 @@
> @cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
> @cm_jt ... ... ........ .. &cmjt %index
>
> +@c_mop ... . ..... ..... .. &cmop %zcmop_n
> +
> # *** RV32/64C Standard Extension (Quadrant 0) ***
> {
> # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
> @@ -140,6 +145,7 @@ sw 110 ... ... .. ... 00 @cs_w
> addi 000 . ..... ..... 01 @ci
> addi 010 . ..... ..... 01 @c_li
> {
> + zcmops 011 0 0...1 00000 01 @c_mop # zcmop carving out of illegal c.lui xn,0 space
> illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
> addi 011 . 00010 ..... 01 @c_addi16sp
> lui 011 . ..... ..... 01 @c_lui
> diff --git a/target/riscv/insn_trans/trans_zimops.c.inc b/target/riscv/insn_trans/trans_zimops.c.inc
> index b5ad7bded8..99f25bd9ea 100644
> --- a/target/riscv/insn_trans/trans_zimops.c.inc
> +++ b/target/riscv/insn_trans/trans_zimops.c.inc
> @@ -48,3 +48,14 @@ static bool trans_zimops_rr(DisasContext *ctx, arg_zimops_r * a)
> gen_set_gpr(ctx, a->rd, dest);
> return true;
> }
> +
> +static bool trans_zcmops(DisasContext *ctx, arg_zcmops * a)
> +{
> + /* zimops not implemented, return false */
> + if (!ctx->cfg_ptr->ext_zimops) {
> + gen_exception_illegal(ctx);
> + return false;
> + }
> +
> + return true;
> +}
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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