From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU
Date: Mon, 1 Jul 2024 11:37:16 +0800 [thread overview]
Message-ID: <20240701033722.954-1-zhiwei_liu@linux.alibaba.com> (raw)
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
- Run RV64 QEMU with RV32 CPU
qemu-system-riscv64 -cpu rv32 -M virt -nographic \
-kernel Image \
-append "root=/dev/vda ro console=ttyS0" \
-drive file=rootfs.ext2,format=raw,id=hd0 \
-device virtio-blk-device,drive=hd0 -netdev user,id=net0 \
-device virtio-net-device,netdev=net0
OpenSBI v1.4
QEMU emulator version 9.0.50 (v9.0.0-1132-g7799dc2e3b)
[ 0.000000] Linux version 6.9.0 (developer@11109ca35736) (riscv32-unknown-linux-gnu-gcc (gc891d8dc23e-dirty) 13.2.0, GNU ld (GNU Binutils) 2.42) #3 SMP Fri May 31 08:42:15 UTC 2024
[ 0.000000] random: crng init done
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80400000
[ 0.000000] Machine model: riscv-virtio,qemu
[ 0.000000] SBI specification v2.0 detected
[ 0.000000] SBI implementation ID=0x1 Version=0x10004
[ 0.000000] SBI TIME extension detected
[ 0.000000] SBI IPI extension detected
[ 0.000000] SBI RFENCE extension detected
[ 0.000000] SBI SRST extension detected
[ 0.000000] SBI DBCN extension detected
[ 0.000000] efi: UEFI not found.
[ 0.000000] OF: reserved mem: 0x80000000..0x8003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000
[ 0.000000] OF: reserved mem: 0x80040000..0x8004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000080400000-0x0000000087ffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080400000-0x0000000087ffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x0000000087ffffff]
[ 0.000000] On node 0, zone Normal: 1024 pages in unavailable ranges
[ 0.000000] SBI HSM extension detected
[ 0.000000] riscv: base ISA extensions acdfhim
[ 0.000000] riscv: ELF capabilities acdfim
[ 0.000000] percpu: Embedded 17 pages/cpu s37728 r8192 d23712 u69632
[ 0.000000] Kernel command line: root=/dev/vda ro console=ttyS0
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 31465
[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] fixmap : 0x9c800000 - 0x9d000000 (8192 kB)
[ 0.000000] pci io : 0x9d000000 - 0x9e000000 ( 16 MB)
[ 0.000000] vmemmap : 0x9e000000 - 0xa0000000 ( 32 MB)
[ 0.000000] vmalloc : 0xa0000000 - 0xc0000000 ( 512 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xc7c00000 ( 124 MB)
[ 0.000000] Memory: 95700K/126976K available (9090K kernel code, 8845K rwdata, 4096K rodata, 4231K init, 341K bss, 31276K reserved, 0K cma-reserved)
...
Welcome to Buildroot
buildroot login: root
# cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv32imafdch_zicbom_zicboz_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfa_zba_zbb_zbc_zbs_sstc
mmu : sv32
TANG Tiancheng (6):
target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Detect sxl to set bit width for RV32 in RV64
target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Enable RV32 CPU support in RV64 QEMU
configs/targets/riscv64-softmmu.mak | 2 +-
hw/riscv/boot.c | 35 +++++++++++++++++++----------
hw/riscv/sifive_u.c | 3 ++-
include/hw/riscv/boot.h | 4 +++-
include/hw/riscv/boot_opensbi.h | 29 ++++++++++++++++++++++++
target/riscv/cpu.c | 17 ++++++++++----
target/riscv/cpu.h | 5 ++++-
target/riscv/cpu_helper.c | 23 ++++++++++++++-----
target/riscv/pmp.c | 2 +-
9 files changed, 93 insertions(+), 27 deletions(-)
--
2.43.0
next reply other threads:[~2024-07-01 3:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-01 3:37 LIU Zhiwei [this message]
2024-07-01 3:37 ` [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-03 2:27 ` Alistair Francis
2024-07-01 3:37 ` [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
2024-07-03 2:28 ` Alistair Francis
2024-07-01 3:37 ` [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
2024-07-01 15:10 ` Philippe Mathieu-Daudé
2024-07-02 1:48 ` LIU Zhiwei
2024-07-01 3:37 ` [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
2024-07-03 2:33 ` Alistair Francis
2024-07-03 2:46 ` LIU Zhiwei
2024-07-01 3:37 ` [PATCH 5/6] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
2024-07-01 3:37 ` [PATCH 6/6] target/riscv: Enable RV32 CPU support " LIU Zhiwei
2024-07-02 14:18 ` [PATCH 0/6] target/riscv: Expose RV32 cpu to " Philippe Mathieu-Daudé
2024-07-03 2:35 ` Alistair Francis
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