From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
Date: Mon, 1 Jul 2024 11:37:18 +0800 [thread overview]
Message-ID: <20240701033722.954-3-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20240701033722.954-1-zhiwei_liu@linux.alibaba.com>
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9eea397e72..f65aa3dba7 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
*/
pmp_size = -(addr | TARGET_PAGE_MASK);
} else {
- pmp_size = sizeof(target_ulong);
+ pmp_size = 2UL << riscv_cpu_mxl(env);
}
} else {
pmp_size = size;
--
2.43.0
next prev parent reply other threads:[~2024-07-01 3:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-01 3:37 [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-01 3:37 ` [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-03 2:27 ` Alistair Francis
2024-07-01 3:37 ` LIU Zhiwei [this message]
2024-07-03 2:28 ` [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 Alistair Francis
2024-07-01 3:37 ` [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
2024-07-01 15:10 ` Philippe Mathieu-Daudé
2024-07-02 1:48 ` LIU Zhiwei
2024-07-01 3:37 ` [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
2024-07-03 2:33 ` Alistair Francis
2024-07-03 2:46 ` LIU Zhiwei
2024-07-01 3:37 ` [PATCH 5/6] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
2024-07-01 3:37 ` [PATCH 6/6] target/riscv: Enable RV32 CPU support " LIU Zhiwei
2024-07-02 14:18 ` [PATCH 0/6] target/riscv: Expose RV32 cpu to " Philippe Mathieu-Daudé
2024-07-03 2:35 ` Alistair Francis
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