Re: [PATCH v2] docs/cxl: fix some typos

[Jonathan Cameron via <qemu-devel@nongnu.org>]

On Wed, 26 Jun 2024 13:34:58 +0900
Hyeongtak Ji <hyeongtak.ji@gmail.com> wrote:

> This patch corrects minor typographical errors to ensure the ASCII art
> aligns with the explanations provided.  Specifically, it fixes an
> incorrect root port reference and removes redundant words.
> 
> Signed-off-by: Hyeongtak Ji <hyeongtak.ji@gmail.com>
LGTM.  If this can go via trivial. If not I'll queue it up in a
few days.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  docs/system/devices/cxl.rst | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index cf0a5143cfe8..a551d95455bc 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -218,17 +218,17 @@ Notes:
>      A complex configuration here, might be to use the following HDM
>      decoders in HB0. HDM0 routes CFMW0 requests to RP0 and hence
>      part of CXL Type3 0. HDM1 routes CFMW0 requests from a
> -    different region of the CFMW0 PA range to RP2 and hence part
> +    different region of the CFMW0 PA range to RP1 and hence part
>      of CXL Type 3 1.  HDM2 routes yet another PA range from within
>      CFMW0 to be interleaved across RP0 and RP1, providing 2 way
>      interleave of part of the memory provided by CXL Type3 0 and
>      CXL Type 3 1. HDM3 routes those interleaved accesses from
>      CFMW1 that target HB0 to RP 0 and another part of the memory of
>      CXL Type 3 0 (as part of a 2 way interleave at the system level
> -    across for example CXL Type3 0 and CXL Type3 2.
> +    across for example CXL Type3 0 and CXL Type3 2).
>      HDM4 is used to enable system wide 4 way interleave across all
>      the present CXL type3 devices, by interleaving those (interleaved)
> -    requests that HB0 receives from from CFMW1 across RP 0 and
> +    requests that HB0 receives from CFMW1 across RP 0 and
>      RP 1 and hence to yet more regions of the memory of the
>      attached Type3 devices.  Note this is a representative subset
>      of the full range of possible HDM decoder configurations in this