* [PULL 0/7] tcg patch queue
@ 2024-07-03 17:42 Richard Henderson
2024-07-03 17:42 ` [PULL 1/7] util/cpuinfo-ppc: Fix building on OpenBSD Richard Henderson
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Richard Henderson @ 2024-07-03 17:42 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 6746482d12da3b6e4d3cdf06481a0027a797f719:
Merge tag 'sdmmc-20240702' of https://github.com/philmd/qemu into staging (2024-07-02 09:52:10 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu tags/pull-tcg-20240703
for you to fetch changes up to a71d9dfbf63db42d6e6ae87fc112d1f5502183bd:
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 (2024-07-03 10:24:12 -0700)
----------------------------------------------------------------
util: cpuinfo portability fixes for FreeBSD and OpenBSD
util: cpuinfo for riscv host
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2
----------------------------------------------------------------
Brad Smith (3):
util/cpuinfo-ppc: Fix building on OpenBSD
util/cpuinfo-ppc: Add FreeBSD support
util/cpuinfo-aarch64: Add OpenBSD support
Richard Henderson (4):
util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
util/cpuinfo-riscv: Support OpenBSD signal frame
util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2
meson.build | 6 ++
host/include/riscv/host/cpuinfo.h | 23 ++++++++
tcg/riscv/tcg-target.h | 46 +++++++--------
tcg/optimize.c | 2 +-
tests/tcg/x86_64/test-2413.c | 30 ++++++++++
util/cpuinfo-aarch64.c | 36 ++++++++++++
util/cpuinfo-ppc.c | 27 ++++++---
util/cpuinfo-riscv.c | 118 ++++++++++++++++++++++++++++++++++++++
tcg/riscv/tcg-target.c.inc | 84 +++------------------------
tests/tcg/x86_64/Makefile.target | 2 +
util/meson.build | 2 +
11 files changed, 266 insertions(+), 110 deletions(-)
create mode 100644 host/include/riscv/host/cpuinfo.h
create mode 100644 tests/tcg/x86_64/test-2413.c
create mode 100644 util/cpuinfo-riscv.c
^ permalink raw reply [flat|nested] 9+ messages in thread* [PULL 1/7] util/cpuinfo-ppc: Fix building on OpenBSD 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson @ 2024-07-03 17:42 ` Richard Henderson 2024-07-03 17:42 ` [PULL 2/7] util/cpuinfo-ppc: Add FreeBSD support Richard Henderson ` (6 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2024-07-03 17:42 UTC (permalink / raw) To: qemu-devel; +Cc: Brad Smith From: Brad Smith <brad@comstyle.com> OpenBSD does not support AT_HWCAP. Signed-off-by: Brad Smith <brad@comstyle.com> Message-Id: <ZnzM1T6Vo1Q0yAH-@humpty.home.comstyle.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- util/cpuinfo-ppc.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c index b2d8893a06..47af55aa0c 100644 --- a/util/cpuinfo-ppc.c +++ b/util/cpuinfo-ppc.c @@ -6,11 +6,13 @@ #include "qemu/osdep.h" #include "host/cpuinfo.h" -#include <asm/cputable.h> -#ifdef CONFIG_GETAUXVAL -# include <sys/auxv.h> -#else -# include "elf.h" +#ifdef CONFIG_LINUX +# include <asm/cputable.h> +# ifdef CONFIG_GETAUXVAL +# include <sys/auxv.h> +# else +# include "elf.h" +# endif #endif unsigned cpuinfo; @@ -19,16 +21,17 @@ unsigned cpuinfo; unsigned __attribute__((constructor)) cpuinfo_init(void) { unsigned info = cpuinfo; - unsigned long hwcap, hwcap2; if (info) { return info; } - hwcap = qemu_getauxval(AT_HWCAP); - hwcap2 = qemu_getauxval(AT_HWCAP2); info = CPUINFO_ALWAYS; +#ifdef CONFIG_LINUX + unsigned long hwcap = qemu_getauxval(AT_HWCAP); + unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); + /* Version numbers are monotonic, and so imply all lower versions. */ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) { info |= CPUINFO_V3_1 | CPUINFO_V3_0 | CPUINFO_V2_07 | CPUINFO_V2_06; @@ -58,6 +61,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) } } } +#endif cpuinfo = info; return info; -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 2/7] util/cpuinfo-ppc: Add FreeBSD support 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson 2024-07-03 17:42 ` [PULL 1/7] util/cpuinfo-ppc: Fix building on OpenBSD Richard Henderson @ 2024-07-03 17:42 ` Richard Henderson 2024-07-03 17:42 ` [PULL 3/7] util/cpuinfo-aarch64: Add OpenBSD support Richard Henderson ` (5 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2024-07-03 17:42 UTC (permalink / raw) To: qemu-devel; +Cc: Brad Smith From: Brad Smith <brad@comstyle.com> Signed-off-by: Brad Smith <brad@comstyle.com> Message-Id: <Zn9cJ3puWr5lIgsg@humpty.home.comstyle.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- util/cpuinfo-ppc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c index 47af55aa0c..1304f9aa80 100644 --- a/util/cpuinfo-ppc.c +++ b/util/cpuinfo-ppc.c @@ -14,6 +14,13 @@ # include "elf.h" # endif #endif +#ifdef __FreeBSD__ +# include <machine/cpu.h> +# ifndef PPC_FEATURE2_ARCH_3_1 +# define PPC_FEATURE2_ARCH_3_1 0 +# endif +# define PPC_FEATURE2_VEC_CRYPTO PPC_FEATURE2_HAS_VEC_CRYPTO +#endif unsigned cpuinfo; @@ -28,7 +35,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) info = CPUINFO_ALWAYS; -#ifdef CONFIG_LINUX +#if defined(CONFIG_LINUX) || defined(__FreeBSD__) unsigned long hwcap = qemu_getauxval(AT_HWCAP); unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 3/7] util/cpuinfo-aarch64: Add OpenBSD support 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson 2024-07-03 17:42 ` [PULL 1/7] util/cpuinfo-ppc: Fix building on OpenBSD Richard Henderson 2024-07-03 17:42 ` [PULL 2/7] util/cpuinfo-ppc: Add FreeBSD support Richard Henderson @ 2024-07-03 17:42 ` Richard Henderson 2024-07-03 17:42 ` [PULL 4/7] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv Richard Henderson ` (4 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2024-07-03 17:42 UTC (permalink / raw) To: qemu-devel; +Cc: Brad Smith From: Brad Smith <brad@comstyle.com> Signed-off-by: Brad Smith <brad@comstyle.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <ZneEh51XKhxgZKpp@humpty.home.comstyle.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- util/cpuinfo-aarch64.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c index 4c8a005715..8ca775a14b 100644 --- a/util/cpuinfo-aarch64.c +++ b/util/cpuinfo-aarch64.c @@ -20,6 +20,12 @@ #ifdef CONFIG_DARWIN # include <sys/sysctl.h> #endif +#ifdef __OpenBSD__ +# include <machine/armreg.h> +# include <machine/cpu.h> +# include <sys/types.h> +# include <sys/sysctl.h> +#endif unsigned cpuinfo; @@ -72,6 +78,36 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) info |= sysctl_for_bool("hw.optional.arm.FEAT_PMULL") * CPUINFO_PMULL; info |= sysctl_for_bool("hw.optional.arm.FEAT_BTI") * CPUINFO_BTI; #endif +#ifdef __OpenBSD__ + int mib[2]; + uint64_t isar0; + uint64_t pfr1; + size_t len; + + mib[0] = CTL_MACHDEP; + mib[1] = CPU_ID_AA64ISAR0; + len = sizeof(isar0); + if (sysctl(mib, 2, &isar0, &len, NULL, 0) != -1) { + if (ID_AA64ISAR0_ATOMIC(isar0) >= ID_AA64ISAR0_ATOMIC_IMPL) { + info |= CPUINFO_LSE; + } + if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_BASE) { + info |= CPUINFO_AES; + } + if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_PMULL) { + info |= CPUINFO_PMULL; + } + } + + mib[0] = CTL_MACHDEP; + mib[1] = CPU_ID_AA64PFR1; + len = sizeof(pfr1); + if (sysctl(mib, 2, &pfr1, &len, NULL, 0) != -1) { + if (ID_AA64PFR1_BT(pfr1) >= ID_AA64PFR1_BT_IMPL) { + info |= CPUINFO_BTI; + } + } +#endif cpuinfo = info; return info; -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 4/7] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson ` (2 preceding siblings ...) 2024-07-03 17:42 ` [PULL 3/7] util/cpuinfo-aarch64: Add OpenBSD support Richard Henderson @ 2024-07-03 17:42 ` Richard Henderson 2024-07-03 17:42 ` [PULL 5/7] util/cpuinfo-riscv: Support OpenBSD signal frame Richard Henderson ` (3 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2024-07-03 17:42 UTC (permalink / raw) To: qemu-devel Cc: LIU Zhiwei, Alistair Francis, Philippe Mathieu-Daudé, Daniel Henrique Barboza Move detection code out of tcg, similar to other hosts. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- host/include/riscv/host/cpuinfo.h | 23 +++++++++ tcg/riscv/tcg-target.h | 46 ++++++++--------- util/cpuinfo-riscv.c | 85 +++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.c.inc | 84 +++--------------------------- util/meson.build | 2 + 5 files changed, 139 insertions(+), 101 deletions(-) create mode 100644 host/include/riscv/host/cpuinfo.h create mode 100644 util/cpuinfo-riscv.c diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h new file mode 100644 index 0000000000..2b00660e36 --- /dev/null +++ b/host/include/riscv/host/cpuinfo.h @@ -0,0 +1,23 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu identification for RISC-V. + */ + +#ifndef HOST_CPUINFO_H +#define HOST_CPUINFO_H + +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_ZBA (1u << 1) +#define CPUINFO_ZBB (1u << 2) +#define CPUINFO_ZICOND (1u << 3) + +/* Initialized with a constructor. */ +extern unsigned cpuinfo; + +/* + * We cannot rely on constructor ordering, so other constructors must + * use the function interface rather than the variable above. + */ +unsigned cpuinfo_init(void); + +#endif /* HOST_CPUINFO_H */ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 2c1b680b93..1a347eaf6e 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -25,6 +25,8 @@ #ifndef RISCV_TCG_TARGET_H #define RISCV_TCG_TARGET_H +#include "host/cpuinfo.h" + #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) @@ -80,18 +82,12 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL -#if defined(__riscv_arch_test) && defined(__riscv_zbb) -# define have_zbb true -#else -extern bool have_zbb; -#endif - /* optional instructions */ #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_div2_i32 0 -#define TCG_TARGET_HAS_rot_i32 have_zbb +#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 @@ -106,17 +102,17 @@ extern bool have_zbb; #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_bswap16_i32 have_zbb -#define TCG_TARGET_HAS_bswap32_i32 have_zbb +#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_andc_i32 have_zbb -#define TCG_TARGET_HAS_orc_i32 have_zbb -#define TCG_TARGET_HAS_eqv_i32 have_zbb +#define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_clz_i32 have_zbb -#define TCG_TARGET_HAS_ctz_i32 have_zbb -#define TCG_TARGET_HAS_ctpop_i32 have_zbb +#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 @@ -125,7 +121,7 @@ extern bool have_zbb; #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_div2_i64 0 -#define TCG_TARGET_HAS_rot_i64 have_zbb +#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 @@ -137,18 +133,18 @@ extern bool have_zbb; #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_bswap16_i64 have_zbb -#define TCG_TARGET_HAS_bswap32_i64 have_zbb -#define TCG_TARGET_HAS_bswap64_i64 have_zbb +#define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_andc_i64 have_zbb -#define TCG_TARGET_HAS_orc_i64 have_zbb -#define TCG_TARGET_HAS_eqv_i64 have_zbb +#define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 have_zbb -#define TCG_TARGET_HAS_ctz_i64 have_zbb -#define TCG_TARGET_HAS_ctpop_i64 have_zbb +#define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c new file mode 100644 index 0000000000..1236ee5fa4 --- /dev/null +++ b/util/cpuinfo-riscv.c @@ -0,0 +1,85 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu identification for RISC-V. + */ + +#include "qemu/osdep.h" +#include "host/cpuinfo.h" + +unsigned cpuinfo; +static volatile sig_atomic_t got_sigill; + +static void sigill_handler(int signo, siginfo_t *si, void *data) +{ + /* Skip the faulty instruction */ + ucontext_t *uc = (ucontext_t *)data; + uc->uc_mcontext.__gregs[REG_PC] += 4; + + got_sigill = 1; +} + +/* Called both as constructor and (possibly) via other constructors. */ +unsigned __attribute__((constructor)) cpuinfo_init(void) +{ + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned info = cpuinfo; + + if (info) { + return info; + } + + /* Test for compile-time settings. */ +#if defined(__riscv_arch_test) && defined(__riscv_zba) + info |= CPUINFO_ZBA; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zbb) + info |= CPUINFO_ZBB; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zicond) + info |= CPUINFO_ZICOND; +#endif + left &= ~info; + + if (left) { + struct sigaction sa_old, sa_new; + + memset(&sa_new, 0, sizeof(sa_new)); + sa_new.sa_flags = SA_SIGINFO; + sa_new.sa_sigaction = sigill_handler; + sigaction(SIGILL, &sa_new, &sa_old); + + if (left & CPUINFO_ZBA) { + /* Probe for Zba: add.uw zero,zero,zero. */ + got_sigill = 0; + asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" + : : : "memory"); + info |= got_sigill ? 0 : CPUINFO_ZBA; + left &= ~CPUINFO_ZBA; + } + + if (left & CPUINFO_ZBB) { + /* Probe for Zbb: andn zero,zero,zero. */ + got_sigill = 0; + asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" + : : : "memory"); + info |= got_sigill ? 0 : CPUINFO_ZBB; + left &= ~CPUINFO_ZBB; + } + + if (left & CPUINFO_ZICOND) { + /* Probe for Zicond: czero.eqz zero,zero,zero. */ + got_sigill = 0; + asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" + : : : "memory"); + info |= got_sigill ? 0 : CPUINFO_ZICOND; + left &= ~CPUINFO_ZICOND; + } + + sigaction(SIGILL, &sa_old, NULL); + assert(left == 0); + } + + info |= CPUINFO_ALWAYS; + cpuinfo = info; + return info; +} diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 639363039b..d334857226 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,20 +113,6 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_A7, }; -#ifndef have_zbb -bool have_zbb; -#endif -#if defined(__riscv_arch_test) && defined(__riscv_zba) -# define have_zba true -#else -static bool have_zba; -#endif -#if defined(__riscv_arch_test) && defined(__riscv_zicond) -# define have_zicond true -#else -static bool have_zicond; -#endif - static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) { tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); @@ -594,7 +580,7 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) { - if (have_zbb) { + if (cpuinfo & CPUINFO_ZBB) { tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO); } else { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); @@ -604,7 +590,7 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { - if (have_zba) { + if (cpuinfo & CPUINFO_ZBA) { tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO); } else { tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); @@ -614,7 +600,7 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { - if (have_zbb) { + if (cpuinfo & CPUINFO_ZBB) { tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0); } else { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); @@ -624,7 +610,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { - if (have_zbb) { + if (cpuinfo & CPUINFO_ZBB) { tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0); } else { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); @@ -1080,7 +1066,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, int tmpflags; TCGReg t; - if (!have_zicond && (!c_cmp2 || cmp2 == 0)) { + if (!(cpuinfo & CPUINFO_ZICOND) && (!c_cmp2 || cmp2 == 0)) { tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2, val1, c_val1, val2, c_val2); return; @@ -1089,7 +1075,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2); t = tmpflags & ~SETCOND_FLAGS; - if (have_zicond) { + if (cpuinfo & CPUINFO_ZICOND) { if (tmpflags & SETCOND_INV) { tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1); } else { @@ -1304,7 +1290,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, /* TLB Hit - translate address using addend. */ if (addr_type != TCG_TYPE_I32) { tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); - } else if (have_zba) { + } else if (cpuinfo & CPUINFO_ZBA) { tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); } else { @@ -1335,7 +1321,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, if (addr_type != TCG_TYPE_I32) { tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG); - } else if (have_zba) { + } else if (cpuinfo & CPUINFO_ZBA) { tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG); } else { @@ -2110,62 +2096,8 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } -static volatile sig_atomic_t got_sigill; - -static void sigill_handler(int signo, siginfo_t *si, void *data) -{ - /* Skip the faulty instruction */ - ucontext_t *uc = (ucontext_t *)data; - uc->uc_mcontext.__gregs[REG_PC] += 4; - - got_sigill = 1; -} - -static void tcg_target_detect_isa(void) -{ -#if !defined(have_zba) || !defined(have_zbb) || !defined(have_zicond) - /* - * TODO: It is expected that this will be determinable via - * linux riscv_hwprobe syscall, not yet merged. - * In the meantime, test via sigill. - */ - - struct sigaction sa_old, sa_new; - - memset(&sa_new, 0, sizeof(sa_new)); - sa_new.sa_flags = SA_SIGINFO; - sa_new.sa_sigaction = sigill_handler; - sigaction(SIGILL, &sa_new, &sa_old); - -#ifndef have_zba - /* Probe for Zba: add.uw zero,zero,zero. */ - got_sigill = 0; - asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" : : : "memory"); - have_zba = !got_sigill; -#endif - -#ifndef have_zbb - /* Probe for Zba: andn zero,zero,zero. */ - got_sigill = 0; - asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" : : : "memory"); - have_zbb = !got_sigill; -#endif - -#ifndef have_zicond - /* Probe for Zicond: czero.eqz zero,zero,zero. */ - got_sigill = 0; - asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" : : : "memory"); - have_zicond = !got_sigill; -#endif - - sigaction(SIGILL, &sa_old, NULL); -#endif -} - static void tcg_target_init(TCGContext *s) { - tcg_target_detect_isa(); - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; diff --git a/util/meson.build b/util/meson.build index 72b505df11..5d8bef9891 100644 --- a/util/meson.build +++ b/util/meson.build @@ -127,4 +127,6 @@ elif cpu == 'loongarch64' util_ss.add(files('cpuinfo-loongarch.c')) elif cpu in ['ppc', 'ppc64'] util_ss.add(files('cpuinfo-ppc.c')) +elif cpu in ['riscv32', 'riscv64'] + util_ss.add(files('cpuinfo-riscv.c')) endif -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 5/7] util/cpuinfo-riscv: Support OpenBSD signal frame 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson ` (3 preceding siblings ...) 2024-07-03 17:42 ` [PULL 4/7] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv Richard Henderson @ 2024-07-03 17:42 ` Richard Henderson 2024-07-03 17:42 ` [PULL 6/7] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall Richard Henderson ` (2 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2024-07-03 17:42 UTC (permalink / raw) To: qemu-devel Cc: Brad Smith, Philippe Mathieu-Daudé, Daniel Henrique Barboza, Alistair Francis Reported-by: Brad Smith <brad@comstyle.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- util/cpuinfo-riscv.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 1236ee5fa4..7dcfbee2ab 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -13,7 +13,14 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) { /* Skip the faulty instruction */ ucontext_t *uc = (ucontext_t *)data; + +#ifdef __linux__ uc->uc_mcontext.__gregs[REG_PC] += 4; +#elif defined(__OpenBSD__) + uc->sc_sepc += 4; +#else +# error Unsupported OS +#endif got_sigill = 1; } -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 6/7] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson ` (4 preceding siblings ...) 2024-07-03 17:42 ` [PULL 5/7] util/cpuinfo-riscv: Support OpenBSD signal frame Richard Henderson @ 2024-07-03 17:42 ` Richard Henderson 2024-07-03 17:42 ` [PULL 7/7] tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 Richard Henderson 2024-07-03 22:36 ` [PULL 0/7] tcg patch queue Richard Henderson 7 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2024-07-03 17:42 UTC (permalink / raw) To: qemu-devel; +Cc: Alistair Francis, Daniel Henrique Barboza With recent linux kernels, there is a syscall to probe for various ISA extensions. These bits were phased in over several kernel releases, so we still require checks for symbol availability. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- meson.build | 6 ++++++ util/cpuinfo-riscv.c | 26 ++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/meson.build b/meson.build index 54e6b09f4f..2f981f936e 100644 --- a/meson.build +++ b/meson.build @@ -2862,6 +2862,12 @@ have_cpuid_h = cc.links(''' }''') config_host_data.set('CONFIG_CPUID_H', have_cpuid_h) +# Don't bother to advertise asm/hwprobe.h for old versions that do +# not contain RISCV_HWPROBE_EXT_ZBA. +config_host_data.set('CONFIG_ASM_HWPROBE_H', + cc.has_header_symbol('asm/hwprobe.h', + 'RISCV_HWPROBE_EXT_ZBA')) + config_host_data.set('CONFIG_AVX2_OPT', get_option('avx2') \ .require(have_cpuid_h, error_message: 'cpuid.h not available, cannot enable AVX2') \ .require(cc.links(''' diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 7dcfbee2ab..497ce12680 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -6,6 +6,11 @@ #include "qemu/osdep.h" #include "host/cpuinfo.h" +#ifdef CONFIG_ASM_HWPROBE_H +#include <asm/hwprobe.h> +#include <sys/syscall.h> +#endif + unsigned cpuinfo; static volatile sig_atomic_t got_sigill; @@ -47,6 +52,27 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif left &= ~info; +#ifdef CONFIG_ASM_HWPROBE_H + if (left) { + /* + * TODO: glibc 2.40 will introduce <sys/hwprobe.h>, which + * provides __riscv_hwprobe and __riscv_hwprobe_one, + * which is a slightly cleaner interface. + */ + struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_IMA_EXT_0 }; + if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0 + && pair.key >= 0) { + info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; + info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); +#ifdef RISCV_HWPROBE_EXT_ZICOND + info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; + left &= ~CPUINFO_ZICOND; +#endif + } + } +#endif /* CONFIG_ASM_HWPROBE_H */ + if (left) { struct sigaction sa_old, sa_new; -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 7/7] tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson ` (5 preceding siblings ...) 2024-07-03 17:42 ` [PULL 6/7] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall Richard Henderson @ 2024-07-03 17:42 ` Richard Henderson 2024-07-03 22:36 ` [PULL 0/7] tcg patch queue Richard Henderson 7 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2024-07-03 17:42 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-stable, Alex Bennée Argument ordering for setcond2 is: output, a_low, a_high, b_low, b_high, cond The test is supposed to be against b_low, not a_high. Cc: qemu-stable@nongnu.org Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240701024623.1265028-1-richard.henderson@linaro.org> --- tcg/optimize.c | 2 +- tests/tcg/x86_64/test-2413.c | 30 ++++++++++++++++++++++++++++++ tests/tcg/x86_64/Makefile.target | 2 ++ 3 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/x86_64/test-2413.c diff --git a/tcg/optimize.c b/tcg/optimize.c index 8886f7037a..ba16ec27e2 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2384,7 +2384,7 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) case TCG_COND_TSTEQ: case TCG_COND_TSTNE: - if (arg_is_const_val(op->args[2], 0)) { + if (arg_is_const_val(op->args[3], 0)) { goto do_setcond_high; } if (arg_is_const_val(op->args[4], 0)) { diff --git a/tests/tcg/x86_64/test-2413.c b/tests/tcg/x86_64/test-2413.c new file mode 100644 index 0000000000..456e5332fc --- /dev/null +++ b/tests/tcg/x86_64/test-2413.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright 2024 Linaro, Ltd. */ +/* See https://gitlab.com/qemu-project/qemu/-/issues/2413 */ + +#include <assert.h> + +void test(unsigned long *a, unsigned long *d, unsigned long c) +{ + asm("xorl %%eax, %%eax\n\t" + "xorl %%edx, %%edx\n\t" + "testb $0x20, %%cl\n\t" + "sete %%al\n\t" + "setne %%dl\n\t" + "shll %%cl, %%eax\n\t" + "shll %%cl, %%edx\n\t" + : "=a"(*a), "=d"(*d) + : "c"(c)); +} + +int main(void) +{ + unsigned long a, c, d; + + for (c = 0; c < 64; c++) { + test(&a, &d, c); + assert(a == (c & 0x20 ? 0 : 1u << (c & 0x1f))); + assert(d == (c & 0x20 ? 1u << (c & 0x1f) : 0)); + } + return 0; +} diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target index 5fedf22117..eda9bd7396 100644 --- a/tests/tcg/x86_64/Makefile.target +++ b/tests/tcg/x86_64/Makefile.target @@ -8,6 +8,8 @@ include $(SRC_PATH)/tests/tcg/i386/Makefile.target +X86_64_TESTS += test-2413 + ifeq ($(filter %-linux-user, $(TARGET)),$(TARGET)) X86_64_TESTS += vsyscall X86_64_TESTS += noexec -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PULL 0/7] tcg patch queue 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson ` (6 preceding siblings ...) 2024-07-03 17:42 ` [PULL 7/7] tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 Richard Henderson @ 2024-07-03 22:36 ` Richard Henderson 7 siblings, 0 replies; 9+ messages in thread From: Richard Henderson @ 2024-07-03 22:36 UTC (permalink / raw) To: qemu-devel On 7/3/24 10:42, Richard Henderson wrote: > The following changes since commit 6746482d12da3b6e4d3cdf06481a0027a797f719: > > Merge tag 'sdmmc-20240702' ofhttps://github.com/philmd/qemu into staging (2024-07-02 09:52:10 -0700) > > are available in the Git repository at: > > https://gitlab.com/rth7680/qemu tags/pull-tcg-20240703 > > for you to fetch changes up to a71d9dfbf63db42d6e6ae87fc112d1f5502183bd: > > tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 (2024-07-03 10:24:12 -0700) > > ---------------------------------------------------------------- > util: cpuinfo portability fixes for FreeBSD and OpenBSD > util: cpuinfo for riscv host > tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~ ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-07-03 22:37 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-07-03 17:42 [PULL 0/7] tcg patch queue Richard Henderson 2024-07-03 17:42 ` [PULL 1/7] util/cpuinfo-ppc: Fix building on OpenBSD Richard Henderson 2024-07-03 17:42 ` [PULL 2/7] util/cpuinfo-ppc: Add FreeBSD support Richard Henderson 2024-07-03 17:42 ` [PULL 3/7] util/cpuinfo-aarch64: Add OpenBSD support Richard Henderson 2024-07-03 17:42 ` [PULL 4/7] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv Richard Henderson 2024-07-03 17:42 ` [PULL 5/7] util/cpuinfo-riscv: Support OpenBSD signal frame Richard Henderson 2024-07-03 17:42 ` [PULL 6/7] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall Richard Henderson 2024-07-03 17:42 ` [PULL 7/7] tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 Richard Henderson 2024-07-03 22:36 ` [PULL 0/7] tcg patch queue Richard Henderson
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