[PATCH 0/2] RISC-V: Add preliminary textra trigger CSR functions

[Alvin Chang via <qemu-devel@nongnu.org>]

According to RISC-V Debug specification, the optional textra32 and textra64
trigger CSRs can be used to configure additional matching conditions for the
triggers.

This series support to write MHVALUE and MHSELECT fields into textra32 and
textra64 trigger CSRs. Besides, the additional matching condition between
textra.MHVALUE and mcontext CSR is also implemented.

Alvin Chang (2):
  target/riscv: Preliminary textra trigger CSR writting support
  target/riscv: Add textra matching condition for the triggers

 target/riscv/cpu_bits.h |  10 +++
 target/riscv/debug.c    | 144 ++++++++++++++++++++++++++++++++++++++--
 target/riscv/debug.h    |   3 +
 3 files changed, 150 insertions(+), 7 deletions(-)

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2.34.1