From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Alistair Francis" <alistair@alistair23.me>,
"Kevin Wolf" <kwolf@redhat.com>,
"Hanna Reitz" <hreitz@redhat.com>,
"Jason Wang" <jasowang@redhat.com>,
"Cleber Rosa" <crosa@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Wainer dos Santos Moschetta" <wainersm@redhat.com>,
"Beraldo Leal" <bleal@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:Block layer core" <qemu-block@nongnu.org>
Cc: jamin_lin@aspeedtech.com, troy_lee@aspeedtech.com,
yunlin.tang@aspeedtech.com, "Cédric Le Goater" <clg@redhat.com>
Subject: [PATCH v3 6/8] hw/block: m25p80: support quad mode for w25q01jvq
Date: Thu, 4 Jul 2024 16:29:20 +0800 [thread overview]
Message-ID: <20240704082922.1464317-7-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240704082922.1464317-1-jamin_lin@aspeedtech.com>
According to the w25q01jv datasheet at page 16,
it is required to set QE bit in "Status Register 2".
Besides, users are able to utilize "Write Status Register 1(0x01)"
command to set QE bit in "Status Register 2" and
utilize "Read Status Register 2(0x35)" command to get the QE bit status.
To support quad mode for w25q01jvq, update collecting data needed
2 bytes for WRSR command in decode_new_cmd function and
verify QE bit at the second byte of collecting data bit 2
in complete_collecting_data.
Update RDCR_EQIO command to set bit 2 of return data
if quad mode enable in decode_new_cmd.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/block/m25p80.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 8dec134832..9e99107b42 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -416,6 +416,7 @@ typedef enum {
/*
* Micron: 0x35 - enable QPI
* Spansion: 0x35 - read control register
+ * Winbond: 0x35 - quad enable
*/
RDCR_EQIO = 0x35,
RSTQIO = 0xf5,
@@ -798,6 +799,11 @@ static void complete_collecting_data(Flash *s)
s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
}
break;
+ case MAN_WINBOND:
+ if (s->len > 1) {
+ s->quad_enable = !!(s->data[1] & 0x02);
+ }
+ break;
default:
break;
}
@@ -1254,6 +1260,10 @@ static void decode_new_cmd(Flash *s, uint32_t value)
s->needed_bytes = 2;
s->state = STATE_COLLECTING_VAR_LEN_DATA;
break;
+ case MAN_WINBOND:
+ s->needed_bytes = 2;
+ s->state = STATE_COLLECTING_VAR_LEN_DATA;
+ break;
default:
s->needed_bytes = 1;
s->state = STATE_COLLECTING_DATA;
@@ -1431,6 +1441,12 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case MAN_MACRONIX:
s->quad_enable = true;
break;
+ case MAN_WINBOND:
+ s->data[0] = (!!s->quad_enable) << 1;
+ s->pos = 0;
+ s->len = 1;
+ s->state = STATE_READING_DATA;
+ break;
default:
break;
}
--
2.34.1
next prev parent reply other threads:[~2024-07-04 8:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-04 8:29 [PATCH v3 0/8] support AST2700 network Jamin Lin via
2024-07-04 8:29 ` [PATCH v3 1/8] hw/net:ftgmac100: update memory region size to 64KB Jamin Lin via
2024-07-04 8:53 ` Cédric Le Goater
2024-07-04 8:29 ` [PATCH v3 2/8] hw/net:ftgmac100: update ring base address to 64 bits Jamin Lin via
2024-07-04 9:08 ` Cédric Le Goater
2024-07-04 8:29 ` [PATCH v3 3/8] hw/net:ftgmac100: introduce TX and RX ring base address high registers to support " Jamin Lin via
2024-07-04 8:54 ` Cédric Le Goater
2024-07-04 8:29 ` [PATCH v3 4/8] hw/net:ftgmac100: update TX and RX packet buffers address to " Jamin Lin via
2024-07-04 9:19 ` Cédric Le Goater
2024-07-04 8:29 ` [PATCH v3 5/8] aspeed/soc: set dma64 property for AST2700 ftgmac100 Jamin Lin via
2024-07-04 8:54 ` Cédric Le Goater
2024-07-04 8:29 ` Jamin Lin via [this message]
2024-07-04 8:29 ` [PATCH v3 7/8] machine_aspeed.py: update to test ASPEED OpenBMC SDK v09.02 for AST2700 Jamin Lin via
2024-07-04 8:54 ` Cédric Le Goater
2024-07-04 8:29 ` [PATCH v3 8/8] machine_aspeed.py: update to test network " Jamin Lin via
2024-07-04 8:54 ` Cédric Le Goater
2024-07-09 9:52 ` [PATCH v3 0/8] support AST2700 network Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240704082922.1464317-7-jamin_lin@aspeedtech.com \
--to=qemu-devel@nongnu.org \
--cc=alistair@alistair23.me \
--cc=andrew@codeconstruct.com.au \
--cc=bleal@redhat.com \
--cc=clg@kaod.org \
--cc=clg@redhat.com \
--cc=crosa@redhat.com \
--cc=hreitz@redhat.com \
--cc=jamin_lin@aspeedtech.com \
--cc=jasowang@redhat.com \
--cc=joel@jms.id.au \
--cc=kwolf@redhat.com \
--cc=leetroy@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-block@nongnu.org \
--cc=steven_lee@aspeedtech.com \
--cc=troy_lee@aspeedtech.com \
--cc=wainersm@redhat.com \
--cc=yunlin.tang@aspeedtech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).