* [PATCH v5 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
@ 2024-07-10 2:24 ` LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
` (7 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-10 2:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 35 ++++++++++++++++++++++-----------
hw/riscv/sifive_u.c | 3 ++-
include/hw/riscv/boot.h | 4 +++-
include/hw/riscv/boot_opensbi.h | 29 +++++++++++++++++++++++++++
4 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 47281ca853..1a2c1ff9e0 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -342,27 +342,33 @@ void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
}
-void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
- hwaddr rom_size, uint32_t reset_vec_size,
+void riscv_rom_copy_firmware_info(MachineState *machine,
+ RISCVHartArrayState *harts,
+ hwaddr rom_base, hwaddr rom_size,
+ uint32_t reset_vec_size,
uint64_t kernel_entry)
{
+ struct fw_dynamic_info32 dinfo32;
struct fw_dynamic_info dinfo;
size_t dinfo_len;
- if (sizeof(dinfo.magic) == 4) {
- dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
- dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
- dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
- dinfo.next_addr = cpu_to_le32(kernel_entry);
+ if (riscv_is_32bit(harts)) {
+ dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
+ dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
+ dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
+ dinfo32.next_addr = cpu_to_le32(kernel_entry);
+ dinfo32.options = 0;
+ dinfo32.boot_hart = 0;
+ dinfo_len = sizeof(dinfo32);
} else {
dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
dinfo.next_addr = cpu_to_le64(kernel_entry);
+ dinfo.options = 0;
+ dinfo.boot_hart = 0;
+ dinfo_len = sizeof(dinfo);
}
- dinfo.options = 0;
- dinfo.boot_hart = 0;
- dinfo_len = sizeof(dinfo);
/**
* copy the dynamic firmware info. This information is specific to
@@ -374,7 +380,10 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
exit(1);
}
- rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
+ rom_add_blob_fixed_as("mrom.finfo",
+ riscv_is_32bit(harts) ?
+ (void *)&dinfo32 : (void *)&dinfo,
+ dinfo_len,
rom_base + reset_vec_size,
&address_space_memory);
}
@@ -430,7 +439,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
rom_base, &address_space_memory);
- riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
+ riscv_rom_copy_firmware_info(machine, harts,
+ rom_base, rom_size,
+ sizeof(reset_vec),
kernel_entry);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index af5f923f54..5010c3eadb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -646,7 +646,8 @@ static void sifive_u_machine_init(MachineState *machine)
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
- riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
+ riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus,
+ memmap[SIFIVE_U_DEV_MROM].base,
memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry);
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index a2e4ae9cb0..806256d23f 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -56,7 +56,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
uint64_t fdt_load_addr);
-void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
+void riscv_rom_copy_firmware_info(MachineState *machine,
+ RISCVHartArrayState *harts,
+ hwaddr rom_base,
hwaddr rom_size,
uint32_t reset_vec_size,
uint64_t kernel_entry);
diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h
index 1b749663dc..18664a174b 100644
--- a/include/hw/riscv/boot_opensbi.h
+++ b/include/hw/riscv/boot_opensbi.h
@@ -58,4 +58,33 @@ struct fw_dynamic_info {
target_long boot_hart;
};
+/** Representation dynamic info passed by previous booting stage */
+struct fw_dynamic_info32 {
+ /** Info magic */
+ int32_t magic;
+ /** Info version */
+ int32_t version;
+ /** Next booting stage address */
+ int32_t next_addr;
+ /** Next booting stage mode */
+ int32_t next_mode;
+ /** Options for OpenSBI library */
+ int32_t options;
+ /**
+ * Preferred boot HART id
+ *
+ * It is possible that the previous booting stage uses same link
+ * address as the FW_DYNAMIC firmware. In this case, the relocation
+ * lottery mechanism can potentially overwrite the previous booting
+ * stage while other HARTs are still running in the previous booting
+ * stage leading to boot-time crash. To avoid this boot-time crash,
+ * the previous booting stage can specify last HART that will jump
+ * to the FW_DYNAMIC firmware as the preferred boot HART.
+ *
+ * To avoid specifying a preferred boot HART, the previous booting
+ * stage can set it to -1UL which will force the FW_DYNAMIC firmware
+ * to use the relocation lottery mechanism.
+ */
+ int32_t boot_hart;
+};
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
@ 2024-07-10 2:24 ` LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-10 2:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9eea397e72..5e74b7220f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
*/
pmp_size = -(addr | TARGET_PAGE_MASK);
} else {
- pmp_size = sizeof(target_ulong);
+ pmp_size = 2 << riscv_cpu_mxl(env);
}
} else {
pmp_size = size;
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
@ 2024-07-10 2:24 ` LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-10 2:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 87742047ce..49de81be7e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -693,8 +693,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
#ifdef CONFIG_USER_ONLY
return env->misa_mxl;
#else
- return get_field(env->mstatus, MSTATUS64_SXL);
+ if (env->misa_mxl != MXL_RV32) {
+ return get_field(env->mstatus, MSTATUS64_SXL);
+ }
#endif
+ return MXL_RV32;
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (2 preceding siblings ...)
2024-07-10 2:24 ` [PATCH v5 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
@ 2024-07-10 2:24 ` LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-10 2:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6709622dd3..4f0ab90ac7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits + widened;
+ int sxlen = 16 << riscv_cpu_sxl(env);
+ int sxlen_bytes = sxlen / 8;
if (first_stage == true) {
target_ulong mask, masked_msbs;
- if (TARGET_LONG_BITS > (va_bits - 1)) {
- mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
+ if (sxlen > (va_bits - 1)) {
+ mask = (1L << (sxlen - (va_bits - 1))) - 1;
} else {
mask = 0;
}
@@ -961,7 +963,7 @@ restart:
int pmp_prot;
int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
- sizeof(target_ulong),
+ sxlen_bytes,
MMU_DATA_LOAD, PRV_S);
if (pmp_ret != TRANSLATE_SUCCESS) {
return TRANSLATE_PMP_FAIL;
@@ -1113,7 +1115,7 @@ restart:
* it is no longer valid and we must re-walk the page table.
*/
MemoryRegion *mr;
- hwaddr l = sizeof(target_ulong), addr1;
+ hwaddr l = sxlen_bytes, addr1;
mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
false, MEMTXATTRS_UNSPECIFIED);
if (memory_region_is_ram(mr)) {
@@ -1125,7 +1127,12 @@ restart:
*/
*pte_pa = pte = updated_pte;
#else
- target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ target_ulong old_pte;
+ if (riscv_cpu_sxl(env) == MXL_RV32) {
+ old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
+ } else {
+ old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ }
if (old_pte != pte) {
goto restart;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (3 preceding siblings ...)
2024-07-10 2:24 ` [PATCH v5 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
@ 2024-07-10 2:24 ` LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 6/7] target/riscv: Enable RV32 CPU support " LIU Zhiwei
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-10 2:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4f0ab90ac7..3eedb26cd9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1673,6 +1673,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong tinst = 0;
target_ulong htval = 0;
target_ulong mtval2 = 0;
+ int sxlen = 0;
+ int mxlen = 0;
if (!async) {
/* set tval to badaddr for traps with address information */
@@ -1799,7 +1801,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
+ sxlen = 16 << riscv_cpu_sxl(env);
+ env->scause = cause | ((target_ulong)async << (sxlen - 1));
env->sepc = env->pc;
env->stval = tval;
env->htval = htval;
@@ -1830,7 +1833,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
- env->mcause = cause | ~(((target_ulong)-1) >> async);
+ mxlen = 16 << riscv_cpu_mxl(env);
+ env->mcause = cause | ((target_ulong)async << (mxlen - 1));
env->mepc = env->pc;
env->mtval = tval;
env->mtval2 = mtval2;
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (4 preceding siblings ...)
2024-07-10 2:24 ` [PATCH v5 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
@ 2024-07-10 2:24 ` LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64 LIU Zhiwei
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-10 2:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17 +++++++++++++----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak
index 917980e63e..6c5de72e03 100644
--- a/configs/targets/riscv64-softmmu.mak
+++ b/configs/targets/riscv64-softmmu.mak
@@ -2,6 +2,6 @@ TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_SUPPORTS_MTTCG=y
TARGET_KVM_HAVE_GUEST_DEBUG=y
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml
# needed by boot.c
TARGET_NEED_FDT=y
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a2640cf259..fdd0f10aa5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -630,8 +630,10 @@ static void rv64e_bare_cpu_init(Object *obj)
riscv_cpu_set_misa_ext(env, RVE);
}
-#else /* !TARGET_RISCV64 */
+#endif /* !TARGET_RISCV64 */
+#if defined(TARGET_RISCV32) || \
+ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
static void rv32_base_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -2944,6 +2946,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init),
+#elif defined(TARGET_RISCV64)
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
+#endif
+
+#if defined(TARGET_RISCV32) || \
+ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
@@ -2951,9 +2960,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
-#elif defined(TARGET_RISCV64)
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init),
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
+#endif
+
+#if defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (5 preceding siblings ...)
2024-07-10 2:24 ` [PATCH v5 6/7] target/riscv: Enable RV32 CPU support " LIU Zhiwei
@ 2024-07-10 2:24 ` LIU Zhiwei
2024-07-12 9:52 ` Daniel Henrique Barboza
2024-07-12 1:34 ` [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU Alistair Francis
2024-07-12 9:57 ` Daniel Henrique Barboza
8 siblings, 1 reply; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-10 2:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot rv32 CPUs.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/avocado/boot_linux_console.py | 38 +++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index c35fc5e9ba..6d2f3b05cb 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -12,6 +12,7 @@
import lzma
import gzip
import shutil
+import time
from avocado import skip
from avocado import skipUnless
@@ -1545,3 +1546,40 @@ def test_xtensa_lx60(self):
"""
tar_hash = '49e88d9933742f0164b60839886c9739cb7a0d34'
self.do_test_advcal_2018('02', tar_hash, 'santas-sleigh-ride.elf')
+
+ def test_riscv64_virt_rv32i(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:virt
+ :avocado: tags=cpu:rv32
+ """
+ kernel_url = ('https://github.com/romanheros/rv32-linux/raw/master/'
+ 'Image32.xz')
+ kernel_hash = 'a7ced5c38722481e0821b7cd70719cf53e46c13b'
+ kernel_path_xz = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ kernel_path = os.path.join(self.workdir, 'kernel.riscv32')
+ archive.lzma_uncompress(kernel_path_xz, kernel_path)
+
+ rootfs_url = ('https://github.com/romanheros/rv32-linux/raw/master/'
+ 'rootfs.ext2.xz')
+ rootfs_hash = 'dc25ab9d4b233e8e0bcf7eb220d56fd2008fe263'
+ rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
+
+ rootfs_path = os.path.join(self.workdir, 'rootfs.riscv32')
+ archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
+
+ self.vm.set_console()
+ kernel_command_line = 'root=/dev/vda ro console=ttyS0'
+ self.vm.add_args('-kernel', kernel_path,
+ '-append', kernel_command_line,
+ '-drive', 'file=' + rootfs_path +
+ ',format=raw,id=hd0,if=none',
+ '-device', 'virtio-blk-device,drive=hd0')
+ self.vm.launch()
+
+ console_pattern = 'Welcome to Buildroot'
+ self.wait_for_console_pattern(console_pattern)
+ exec_command(self, 'root')
+ time.sleep(0.1)
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', 'rv32i')
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64
2024-07-10 2:24 ` [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64 LIU Zhiwei
@ 2024-07-12 9:52 ` Daniel Henrique Barboza
2024-07-15 1:29 ` LIU Zhiwei
0 siblings, 1 reply; 14+ messages in thread
From: Daniel Henrique Barboza @ 2024-07-12 9:52 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, bmeng.cn,
TANG Tiancheng
On 7/9/24 11:24 PM, LIU Zhiwei wrote:
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> To regularly test booting Linux with rv32 on QEMU RV64,
> we have added a test to boot_linux_console.py to retrieve
> cpuinfo and verify if it shows 'rv32' when using RV64 to
> boot rv32 CPUs.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> tests/avocado/boot_linux_console.py | 38 +++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
> index c35fc5e9ba..6d2f3b05cb 100644
> --- a/tests/avocado/boot_linux_console.py
> +++ b/tests/avocado/boot_linux_console.py
> @@ -12,6 +12,7 @@
> import lzma
> import gzip
> import shutil
> +import time
>
> from avocado import skip
> from avocado import skipUnless
> @@ -1545,3 +1546,40 @@ def test_xtensa_lx60(self):
> """
> tar_hash = '49e88d9933742f0164b60839886c9739cb7a0d34'
> self.do_test_advcal_2018('02', tar_hash, 'santas-sleigh-ride.elf')
> +
> + def test_riscv64_virt_rv32i(self):
> + """
> + :avocado: tags=arch:riscv64
> + :avocado: tags=machine:virt
> + :avocado: tags=cpu:rv32
> + """
> + kernel_url = ('https://github.com/romanheros/rv32-linux/raw/master/'
> + 'Image32.xz')
> + kernel_hash = 'a7ced5c38722481e0821b7cd70719cf53e46c13b'
> + kernel_path_xz = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
> +
> + kernel_path = os.path.join(self.workdir, 'kernel.riscv32')
> + archive.lzma_uncompress(kernel_path_xz, kernel_path)
> +
> + rootfs_url = ('https://github.com/romanheros/rv32-linux/raw/master/'
> + 'rootfs.ext2.xz')
> + rootfs_hash = 'dc25ab9d4b233e8e0bcf7eb220d56fd2008fe263'
> + rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
> +
> + rootfs_path = os.path.join(self.workdir, 'rootfs.riscv32')
> + archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
> +
> + self.vm.set_console()
> + kernel_command_line = 'root=/dev/vda ro console=ttyS0'
> + self.vm.add_args('-kernel', kernel_path,
> + '-append', kernel_command_line,
> + '-drive', 'file=' + rootfs_path +
> + ',format=raw,id=hd0,if=none',
> + '-device', 'virtio-blk-device,drive=hd0')
> + self.vm.launch()
> +
> + console_pattern = 'Welcome to Buildroot'
> + self.wait_for_console_pattern(console_pattern)
> + exec_command(self, 'root')
> + time.sleep(0.1)
> + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', 'rv32i')
Nothing wrong with adding a boot_linux_console.py, but if we could add a tuxrun_baselines.py
testsuite instead I think it would be great.
I believe Tuxboot is now the preferable way of testing a distro up to boot in QEMU. We have
all other RISC-V CPU boards and CPUs tested in that framework. It's also faster to run.
Here's a diff adding it:
$ git diff
diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
index 736e4aa289..589c7f254b 100644
--- a/tests/avocado/tuxrun_baselines.py
+++ b/tests/avocado/tuxrun_baselines.py
@@ -533,6 +533,22 @@ def test_riscv64_maxcpu(self):
self.common_tuxrun(csums=sums)
+ def test_riscv64_rv32(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:virt
+ :avocado: tags=tuxboot:riscv32
+ :avocado: tags=cpu:rv32
+ """
+ sums = { "Image" :
+ "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
+ "fw_jump.elf" :
+ "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
+ "rootfs.ext4.zst" :
+ "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
+
+ self.common_tuxrun(csums=sums)
+
def test_s390(self):
"""
:avocado: tags=arch:s390x
$ make check-avocado
(...)
(01/21) tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i: PASS (22.32 s)
(...)
(14/21) tests/avocado/tuxrun_baselines.py:TuxRunBaselineTest.test_riscv64_rv32: PASS (10.34 s)
Thanks,
Daniel
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64
2024-07-12 9:52 ` Daniel Henrique Barboza
@ 2024-07-15 1:29 ` LIU Zhiwei
2024-07-15 8:42 ` Daniel Henrique Barboza
0 siblings, 1 reply; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-15 1:29 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, bmeng.cn,
TANG Tiancheng
On 2024/7/12 17:52, Daniel Henrique Barboza wrote:
>
>
> On 7/9/24 11:24 PM, LIU Zhiwei wrote:
>> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>>
>> To regularly test booting Linux with rv32 on QEMU RV64,
>> we have added a test to boot_linux_console.py to retrieve
>> cpuinfo and verify if it shows 'rv32' when using RV64 to
>> boot rv32 CPUs.
>>
>> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
>> Acked-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> tests/avocado/boot_linux_console.py | 38 +++++++++++++++++++++++++++++
>> 1 file changed, 38 insertions(+)
>>
>> diff --git a/tests/avocado/boot_linux_console.py
>> b/tests/avocado/boot_linux_console.py
>> index c35fc5e9ba..6d2f3b05cb 100644
>> --- a/tests/avocado/boot_linux_console.py
>> +++ b/tests/avocado/boot_linux_console.py
>> @@ -12,6 +12,7 @@
>> import lzma
>> import gzip
>> import shutil
>> +import time
>> from avocado import skip
>> from avocado import skipUnless
>> @@ -1545,3 +1546,40 @@ def test_xtensa_lx60(self):
>> """
>> tar_hash = '49e88d9933742f0164b60839886c9739cb7a0d34'
>> self.do_test_advcal_2018('02', tar_hash,
>> 'santas-sleigh-ride.elf')
>> +
>> + def test_riscv64_virt_rv32i(self):
>> + """
>> + :avocado: tags=arch:riscv64
>> + :avocado: tags=machine:virt
>> + :avocado: tags=cpu:rv32
>> + """
>> + kernel_url =
>> ('https://github.com/romanheros/rv32-linux/raw/master/'
>> + 'Image32.xz')
>> + kernel_hash = 'a7ced5c38722481e0821b7cd70719cf53e46c13b'
>> + kernel_path_xz = self.fetch_asset(kernel_url,
>> asset_hash=kernel_hash)
>> +
>> + kernel_path = os.path.join(self.workdir, 'kernel.riscv32')
>> + archive.lzma_uncompress(kernel_path_xz, kernel_path)
>> +
>> + rootfs_url =
>> ('https://github.com/romanheros/rv32-linux/raw/master/'
>> + 'rootfs.ext2.xz')
>> + rootfs_hash = 'dc25ab9d4b233e8e0bcf7eb220d56fd2008fe263'
>> + rootfs_path_xz = self.fetch_asset(rootfs_url,
>> asset_hash=rootfs_hash)
>> +
>> + rootfs_path = os.path.join(self.workdir, 'rootfs.riscv32')
>> + archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
>> +
>> + self.vm.set_console()
>> + kernel_command_line = 'root=/dev/vda ro console=ttyS0'
>> + self.vm.add_args('-kernel', kernel_path,
>> + '-append', kernel_command_line,
>> + '-drive', 'file=' + rootfs_path +
>> + ',format=raw,id=hd0,if=none',
>> + '-device', 'virtio-blk-device,drive=hd0')
>> + self.vm.launch()
>> +
>> + console_pattern = 'Welcome to Buildroot'
>> + self.wait_for_console_pattern(console_pattern)
>> + exec_command(self, 'root')
>> + time.sleep(0.1)
>> + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
>> 'rv32i')
>
>
> Nothing wrong with adding a boot_linux_console.py, but if we could add
> a tuxrun_baselines.py
> testsuite instead I think it would be great.
>
> I believe Tuxboot is now the preferable way of testing a distro up to
> boot in QEMU. We have
> all other RISC-V CPU boards and CPUs tested in that framework. It's
> also faster to run.
>
> Here's a diff adding it:
>
> $ git diff
> diff --git a/tests/avocado/tuxrun_baselines.py
> b/tests/avocado/tuxrun_baselines.py
> index 736e4aa289..589c7f254b 100644
> --- a/tests/avocado/tuxrun_baselines.py
> +++ b/tests/avocado/tuxrun_baselines.py
> @@ -533,6 +533,22 @@ def test_riscv64_maxcpu(self):
>
> self.common_tuxrun(csums=sums)
>
> + def test_riscv64_rv32(self):
> + """
> + :avocado: tags=arch:riscv64
> + :avocado: tags=machine:virt
> + :avocado: tags=tuxboot:riscv32
> + :avocado: tags=cpu:rv32
> + """
> + sums = { "Image" :
> + "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
> + "fw_jump.elf" :
> + "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
> + "rootfs.ext4.zst" :
> + "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
> +
> + self.common_tuxrun(csums=sums)
> +
> def test_s390(self):
> """
> :avocado: tags=arch:s390x
>
>
> $ make check-avocado
> (...)
> (01/21)
> tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i:
> PASS (22.32 s)
> (...)
> (14/21)
> tests/avocado/tuxrun_baselines.py:TuxRunBaselineTest.test_riscv64_rv32:
> PASS (10.34 s)
Hi Daniel,
Thanks for sharing this test way to us. I'd like to replace our test
with yours. And this commit will be authored to you.
Thanks,
Zhiwei
>
>
>
> Thanks,
>
> Daniel
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64
2024-07-15 1:29 ` LIU Zhiwei
@ 2024-07-15 8:42 ` Daniel Henrique Barboza
0 siblings, 0 replies; 14+ messages in thread
From: Daniel Henrique Barboza @ 2024-07-15 8:42 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, bmeng.cn,
TANG Tiancheng
On 7/14/24 10:29 PM, LIU Zhiwei wrote:
>
> On 2024/7/12 17:52, Daniel Henrique Barboza wrote:
>>
>>
>> On 7/9/24 11:24 PM, LIU Zhiwei wrote:
>>> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>>>
>>> To regularly test booting Linux with rv32 on QEMU RV64,
>>> we have added a test to boot_linux_console.py to retrieve
>>> cpuinfo and verify if it shows 'rv32' when using RV64 to
>>> boot rv32 CPUs.
>>>
>>> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>>> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
>>> Acked-by: Alistair Francis <alistair.francis@wdc.com>
>>> ---
>>> tests/avocado/boot_linux_console.py | 38 +++++++++++++++++++++++++++++
>>> 1 file changed, 38 insertions(+)
>>>
>>> diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
>>> index c35fc5e9ba..6d2f3b05cb 100644
>>> --- a/tests/avocado/boot_linux_console.py
>>> +++ b/tests/avocado/boot_linux_console.py
>>> @@ -12,6 +12,7 @@
>>> import lzma
>>> import gzip
>>> import shutil
>>> +import time
>>> from avocado import skip
>>> from avocado import skipUnless
>>> @@ -1545,3 +1546,40 @@ def test_xtensa_lx60(self):
>>> """
>>> tar_hash = '49e88d9933742f0164b60839886c9739cb7a0d34'
>>> self.do_test_advcal_2018('02', tar_hash, 'santas-sleigh-ride.elf')
>>> +
>>> + def test_riscv64_virt_rv32i(self):
>>> + """
>>> + :avocado: tags=arch:riscv64
>>> + :avocado: tags=machine:virt
>>> + :avocado: tags=cpu:rv32
>>> + """
>>> + kernel_url = ('https://github.com/romanheros/rv32-linux/raw/master/'
>>> + 'Image32.xz')
>>> + kernel_hash = 'a7ced5c38722481e0821b7cd70719cf53e46c13b'
>>> + kernel_path_xz = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
>>> +
>>> + kernel_path = os.path.join(self.workdir, 'kernel.riscv32')
>>> + archive.lzma_uncompress(kernel_path_xz, kernel_path)
>>> +
>>> + rootfs_url = ('https://github.com/romanheros/rv32-linux/raw/master/'
>>> + 'rootfs.ext2.xz')
>>> + rootfs_hash = 'dc25ab9d4b233e8e0bcf7eb220d56fd2008fe263'
>>> + rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
>>> +
>>> + rootfs_path = os.path.join(self.workdir, 'rootfs.riscv32')
>>> + archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
>>> +
>>> + self.vm.set_console()
>>> + kernel_command_line = 'root=/dev/vda ro console=ttyS0'
>>> + self.vm.add_args('-kernel', kernel_path,
>>> + '-append', kernel_command_line,
>>> + '-drive', 'file=' + rootfs_path +
>>> + ',format=raw,id=hd0,if=none',
>>> + '-device', 'virtio-blk-device,drive=hd0')
>>> + self.vm.launch()
>>> +
>>> + console_pattern = 'Welcome to Buildroot'
>>> + self.wait_for_console_pattern(console_pattern)
>>> + exec_command(self, 'root')
>>> + time.sleep(0.1)
>>> + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', 'rv32i')
>>
>>
>> Nothing wrong with adding a boot_linux_console.py, but if we could add a tuxrun_baselines.py
>> testsuite instead I think it would be great.
>>
>> I believe Tuxboot is now the preferable way of testing a distro up to boot in QEMU. We have
>> all other RISC-V CPU boards and CPUs tested in that framework. It's also faster to run.
>>
>> Here's a diff adding it:
>>
>> $ git diff
>> diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
>> index 736e4aa289..589c7f254b 100644
>> --- a/tests/avocado/tuxrun_baselines.py
>> +++ b/tests/avocado/tuxrun_baselines.py
>> @@ -533,6 +533,22 @@ def test_riscv64_maxcpu(self):
>>
>> self.common_tuxrun(csums=sums)
>>
>> + def test_riscv64_rv32(self):
>> + """
>> + :avocado: tags=arch:riscv64
>> + :avocado: tags=machine:virt
>> + :avocado: tags=tuxboot:riscv32
>> + :avocado: tags=cpu:rv32
>> + """
>> + sums = { "Image" :
>> + "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
>> + "fw_jump.elf" :
>> + "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
>> + "rootfs.ext4.zst" :
>> + "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
>> +
>> + self.common_tuxrun(csums=sums)
>> +
>> def test_s390(self):
>> """
>> :avocado: tags=arch:s390x
>>
>>
>> $ make check-avocado
>> (...)
>> (01/21) tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i: PASS (22.32 s)
>> (...)
>> (14/21) tests/avocado/tuxrun_baselines.py:TuxRunBaselineTest.test_riscv64_rv32: PASS (10.34 s)
>
> Hi Daniel,
>
> Thanks for sharing this test way to us. I'd like to replace our test with yours. And this commit will be authored to you.
Feel free to use this diff. A "Suggested-by" reference in my name is enough :D
Thanks,
Daniel
>
> Thanks,
> Zhiwei
>
>>
>>
>>
>> Thanks,
>>
>> Daniel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (6 preceding siblings ...)
2024-07-10 2:24 ` [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64 LIU Zhiwei
@ 2024-07-12 1:34 ` Alistair Francis
2024-07-12 9:57 ` Daniel Henrique Barboza
8 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2024-07-12 1:34 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, dbarboza,
liwei1518, bmeng.cn, 甲一
On Wed, Jul 10, 2024 at 12:27 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> From: 甲一 <lzw194868@alibaba-inc.com>
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
> And add an avocado test in tests/avocado.
>
> # make check-avocado AVOCADO_TESTS=/home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> VENVPIP install -e /home/jenkins/git/qemu/python/
> /home/jenkins/git/qemu/build/pyvenv/bin/python3 -B /home/jenkins/git/qemu/python/scripts/mkvenv.py ensuregroup --online /home/jenkins/git/qemu/pythondeps.toml avocado
> mkvenv: checking for avocado-framework(>=88.1, <93.0)
> mkvenv: checking for pycdlib>=1.11.0
> mkvenv: installing avocado-framework==88.1, pycdlib>=1.11.0
> AVOCADO tests/avocado
> Fetching asset from /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> Fetching asset from /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> JOB ID : 8c2e1ff918d3111d078a52eba9956893afaf9e1d
> JOB LOG : /home/jenkins/git/qemu/build/tests/results/job-2024-07-10T09.55-8c2e1ff/job.log
> (1/1) /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i: PASS (17.50 s)
> RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
> JOB TIME : 29.50 s
>
> v5:
> Rebase to master and add tags
>
> v4:
> Drop UL completely in PATCH v3 2/7, 4/7, 5/7.
> Avocado: Add "if=none" to "-drive" option in QEMU command line
>
> v3:
> Rebase to the master branch
>
> v2:
> Remove the line that was inadvertently left in PATCH v1 4/6.
> Add an avocado test.
>
> v1:
> https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
>
> TANG Tiancheng (7):
> target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
> target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
> target/riscv: Correct SXL return value for RV32 in RV64 QEMU
> target/riscv: Detect sxl to set bit width for RV32 in RV64
> target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
> target/riscv: Enable RV32 CPU support in RV64 QEMU
> tests/avocado: Add an avocado test for riscv64
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> configs/targets/riscv64-softmmu.mak | 2 +-
> hw/riscv/boot.c | 35 +++++++++++++++++---------
> hw/riscv/sifive_u.c | 3 ++-
> include/hw/riscv/boot.h | 4 ++-
> include/hw/riscv/boot_opensbi.h | 29 ++++++++++++++++++++++
> target/riscv/cpu.c | 17 ++++++++++---
> target/riscv/cpu.h | 5 +++-
> target/riscv/cpu_helper.c | 25 +++++++++++++------
> target/riscv/pmp.c | 2 +-
> tests/avocado/boot_linux_console.py | 38 +++++++++++++++++++++++++++++
> 10 files changed, 132 insertions(+), 28 deletions(-)
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (7 preceding siblings ...)
2024-07-12 1:34 ` [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU Alistair Francis
@ 2024-07-12 9:57 ` Daniel Henrique Barboza
2024-07-15 1:31 ` LIU Zhiwei
8 siblings, 1 reply; 14+ messages in thread
From: Daniel Henrique Barboza @ 2024-07-12 9:57 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, bmeng.cn,
甲一
On 7/9/24 11:24 PM, LIU Zhiwei wrote:
> From: 甲一 <lzw194868@alibaba-inc.com>
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
> And add an avocado test in tests/avocado.
Thanks for this work and sorry for the late review.
One thing to look out as a follow-up is the 'max' CPU. It has the same name
in both 32 and 64 bits so it'll result in a conflict with the 'max' CPU for
rv64.
One easy way out is to add a new 'max32' bit CPU for riscv32, which would be an
alias for the 'max' CPU, then adding 'max32' support in rv64.
Thanks,
Daniel
>
> # make check-avocado AVOCADO_TESTS=/home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> VENVPIP install -e /home/jenkins/git/qemu/python/
> /home/jenkins/git/qemu/build/pyvenv/bin/python3 -B /home/jenkins/git/qemu/python/scripts/mkvenv.py ensuregroup --online /home/jenkins/git/qemu/pythondeps.toml avocado
> mkvenv: checking for avocado-framework(>=88.1, <93.0)
> mkvenv: checking for pycdlib>=1.11.0
> mkvenv: installing avocado-framework==88.1, pycdlib>=1.11.0
> AVOCADO tests/avocado
> Fetching asset from /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> Fetching asset from /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> JOB ID : 8c2e1ff918d3111d078a52eba9956893afaf9e1d
> JOB LOG : /home/jenkins/git/qemu/build/tests/results/job-2024-07-10T09.55-8c2e1ff/job.log
> (1/1) /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i: PASS (17.50 s)
> RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
> JOB TIME : 29.50 s
>
> v5:
> Rebase to master and add tags
>
> v4:
> Drop UL completely in PATCH v3 2/7, 4/7, 5/7.
> Avocado: Add "if=none" to "-drive" option in QEMU command line
>
> v3:
> Rebase to the master branch
>
> v2:
> Remove the line that was inadvertently left in PATCH v1 4/6.
> Add an avocado test.
>
> v1:
> https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
>
> TANG Tiancheng (7):
> target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
> target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
> target/riscv: Correct SXL return value for RV32 in RV64 QEMU
> target/riscv: Detect sxl to set bit width for RV32 in RV64
> target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
> target/riscv: Enable RV32 CPU support in RV64 QEMU
> tests/avocado: Add an avocado test for riscv64
>
> configs/targets/riscv64-softmmu.mak | 2 +-
> hw/riscv/boot.c | 35 +++++++++++++++++---------
> hw/riscv/sifive_u.c | 3 ++-
> include/hw/riscv/boot.h | 4 ++-
> include/hw/riscv/boot_opensbi.h | 29 ++++++++++++++++++++++
> target/riscv/cpu.c | 17 ++++++++++---
> target/riscv/cpu.h | 5 +++-
> target/riscv/cpu_helper.c | 25 +++++++++++++------
> target/riscv/pmp.c | 2 +-
> tests/avocado/boot_linux_console.py | 38 +++++++++++++++++++++++++++++
> 10 files changed, 132 insertions(+), 28 deletions(-)
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
2024-07-12 9:57 ` Daniel Henrique Barboza
@ 2024-07-15 1:31 ` LIU Zhiwei
0 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-07-15 1:31 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, bmeng.cn,
甲一
On 2024/7/12 17:57, Daniel Henrique Barboza wrote:
>
>
> On 7/9/24 11:24 PM, LIU Zhiwei wrote:
>> From: 甲一 <lzw194868@alibaba-inc.com>
>>
>> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
>> qemu-system-riscv64 can directly boot a RV32 Linux.
>>
>> This patch set has been tested with 6.9.0 Linux Image.
>> And add an avocado test in tests/avocado.
>
> Thanks for this work and sorry for the late review.
>
> One thing to look out as a follow-up is the 'max' CPU. It has the same
> name
> in both 32 and 64 bits so it'll result in a conflict with the 'max'
> CPU for
> rv64.
>
> One easy way out is to add a new 'max32' bit CPU for riscv32, which
> would be an
> alias for the 'max' CPU, then adding 'max32' support in rv64.
I think it is good. One question is if we should also add any32 cpu for
rv64, which has the similar conflict of 'max' CPU.
Thanks,
Zhiwei
>
>
> Thanks,
>
> Daniel
>
>
>>
>> # make check-avocado
>> AVOCADO_TESTS=/home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
>> VENVPIP install -e /home/jenkins/git/qemu/python/
>> /home/jenkins/git/qemu/build/pyvenv/bin/python3 -B
>> /home/jenkins/git/qemu/python/scripts/mkvenv.py ensuregroup --online
>> /home/jenkins/git/qemu/pythondeps.toml avocado
>> mkvenv: checking for avocado-framework(>=88.1, <93.0)
>> mkvenv: checking for pycdlib>=1.11.0
>> mkvenv: installing avocado-framework==88.1, pycdlib>=1.11.0
>> AVOCADO tests/avocado
>> Fetching asset from
>> /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
>> Fetching asset from
>> /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
>> JOB ID : 8c2e1ff918d3111d078a52eba9956893afaf9e1d
>> JOB LOG :
>> /home/jenkins/git/qemu/build/tests/results/job-2024-07-10T09.55-8c2e1ff/job.log
>> (1/1)
>> /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i:
>> PASS (17.50 s)
>> RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT
>> 0 | CANCEL 0
>> JOB TIME : 29.50 s
>>
>> v5:
>> Rebase to master and add tags
>>
>> v4:
>> Drop UL completely in PATCH v3 2/7, 4/7, 5/7.
>> Avocado: Add "if=none" to "-drive" option in QEMU command line
>>
>> v3:
>> Rebase to the master branch
>>
>> v2:
>> Remove the line that was inadvertently left in PATCH v1 4/6.
>> Add an avocado test.
>>
>> v1:
>> https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
>>
>> TANG Tiancheng (7):
>> target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
>> target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
>> target/riscv: Correct SXL return value for RV32 in RV64 QEMU
>> target/riscv: Detect sxl to set bit width for RV32 in RV64
>> target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
>> target/riscv: Enable RV32 CPU support in RV64 QEMU
>> tests/avocado: Add an avocado test for riscv64
>>
>> configs/targets/riscv64-softmmu.mak | 2 +-
>> hw/riscv/boot.c | 35 +++++++++++++++++---------
>> hw/riscv/sifive_u.c | 3 ++-
>> include/hw/riscv/boot.h | 4 ++-
>> include/hw/riscv/boot_opensbi.h | 29 ++++++++++++++++++++++
>> target/riscv/cpu.c | 17 ++++++++++---
>> target/riscv/cpu.h | 5 +++-
>> target/riscv/cpu_helper.c | 25 +++++++++++++------
>> target/riscv/pmp.c | 2 +-
>> tests/avocado/boot_linux_console.py | 38 +++++++++++++++++++++++++++++
>> 10 files changed, 132 insertions(+), 28 deletions(-)
>>
^ permalink raw reply [flat|nested] 14+ messages in thread