From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
zhiwei_liu@linux.alibaba.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: [PATCH v5 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
Date: Wed, 10 Jul 2024 10:24:25 +0800 [thread overview]
Message-ID: <20240710022430.1306-3-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20240710022430.1306-1-zhiwei_liu@linux.alibaba.com>
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9eea397e72..5e74b7220f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
*/
pmp_size = -(addr | TARGET_PAGE_MASK);
} else {
- pmp_size = sizeof(target_ulong);
+ pmp_size = 2 << riscv_cpu_mxl(env);
}
} else {
pmp_size = size;
--
2.25.1
next prev parent reply other threads:[~2024-07-10 2:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-10 2:24 ` LIU Zhiwei [this message]
2024-07-10 2:24 ` [PATCH v5 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 6/7] target/riscv: Enable RV32 CPU support " LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64 LIU Zhiwei
2024-07-12 9:52 ` Daniel Henrique Barboza
2024-07-15 1:29 ` LIU Zhiwei
2024-07-15 8:42 ` Daniel Henrique Barboza
2024-07-12 1:34 ` [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU Alistair Francis
2024-07-12 9:57 ` Daniel Henrique Barboza
2024-07-15 1:31 ` LIU Zhiwei
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