From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
zhiwei_liu@linux.alibaba.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: [PATCH v5 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64
Date: Wed, 10 Jul 2024 10:24:27 +0800 [thread overview]
Message-ID: <20240710022430.1306-5-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20240710022430.1306-1-zhiwei_liu@linux.alibaba.com>
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6709622dd3..4f0ab90ac7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits + widened;
+ int sxlen = 16 << riscv_cpu_sxl(env);
+ int sxlen_bytes = sxlen / 8;
if (first_stage == true) {
target_ulong mask, masked_msbs;
- if (TARGET_LONG_BITS > (va_bits - 1)) {
- mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
+ if (sxlen > (va_bits - 1)) {
+ mask = (1L << (sxlen - (va_bits - 1))) - 1;
} else {
mask = 0;
}
@@ -961,7 +963,7 @@ restart:
int pmp_prot;
int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
- sizeof(target_ulong),
+ sxlen_bytes,
MMU_DATA_LOAD, PRV_S);
if (pmp_ret != TRANSLATE_SUCCESS) {
return TRANSLATE_PMP_FAIL;
@@ -1113,7 +1115,7 @@ restart:
* it is no longer valid and we must re-walk the page table.
*/
MemoryRegion *mr;
- hwaddr l = sizeof(target_ulong), addr1;
+ hwaddr l = sxlen_bytes, addr1;
mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
false, MEMTXATTRS_UNSPECIFIED);
if (memory_region_is_ram(mr)) {
@@ -1125,7 +1127,12 @@ restart:
*/
*pte_pa = pte = updated_pte;
#else
- target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ target_ulong old_pte;
+ if (riscv_cpu_sxl(env) == MXL_RV32) {
+ old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
+ } else {
+ old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ }
if (old_pte != pte) {
goto restart;
}
--
2.25.1
next prev parent reply other threads:[~2024-07-10 2:28 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` LIU Zhiwei [this message]
2024-07-10 2:24 ` [PATCH v5 5/7] target/riscv: Correct mcause/scause bit width " LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 6/7] target/riscv: Enable RV32 CPU support " LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64 LIU Zhiwei
2024-07-12 9:52 ` Daniel Henrique Barboza
2024-07-15 1:29 ` LIU Zhiwei
2024-07-15 8:42 ` Daniel Henrique Barboza
2024-07-12 1:34 ` [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU Alistair Francis
2024-07-12 9:57 ` Daniel Henrique Barboza
2024-07-15 1:31 ` LIU Zhiwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240710022430.1306-5-zhiwei_liu@linux.alibaba.com \
--to=zhiwei_liu@linux.alibaba.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng.cn@gmail.com \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=tangtiancheng.ttc@alibaba-inc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).