From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Subject: [PATCH 1/1] target/arm: calculate cache sizes properly
Date: Wed, 10 Jul 2024 19:35:12 +0200 [thread overview]
Message-ID: <20240710173512.424547-1-marcin.juszkiewicz@linaro.org> (raw)
Neoverse-V1 TRM says that NumSets are [27:13] not :32 like in code.
With this fix all cores which use make_ccsidr64() function have proper
size of cpu caches.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
target/arm/tcg/cpu64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index fe232eb306..98144e1d20 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -50,7 +50,7 @@ static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
sets = cachesize / (assoc * linesize);
assert(cachesize % (assoc * linesize) == 0);
- return ((uint64_t)(sets - 1) << 32)
+ return ((uint64_t)(sets - 1) << 13)
| ((assoc - 1) << 3)
| (lg_linesize - 4);
}
--
2.45.2
next reply other threads:[~2024-07-10 17:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 17:35 Marcin Juszkiewicz [this message]
2024-07-11 10:19 ` [PATCH 1/1] target/arm: calculate cache sizes properly Peter Maydell
2024-07-11 10:45 ` Marcin Juszkiewicz
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