From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-devel@nongnu.org
Subject: [PATCH 01/18] target/ppc: Fix msgsnd for POWER8
Date: Fri, 12 Jul 2024 00:18:33 +1000 [thread overview]
Message-ID: <20240711141851.406677-2-npiggin@gmail.com> (raw)
In-Reply-To: <20240711141851.406677-1-npiggin@gmail.com>
POWER8 (ISA v2.07S) introduced the doorbell facility, the msgsnd
instruction behaved mostly like msgsndp, it was addressed by TIR
and could only send interrupts between threads on the core.
ISA v3.0 changed msgsnd to be addressed by PIR and can interrupt
any thread in the system.
msgsnd only implements the v3.0 semantics, which can make
multi-threaded POWER8 hang when booting Linux (due to IPIs
failing). This change adds v2.07 semantics.
---
target/ppc/excp_helper.c | 74 ++++++++++++++++++++++++----------------
1 file changed, 44 insertions(+), 30 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0cd542675f..c0120c8a88 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2998,6 +2998,41 @@ static inline bool dbell_bcast_subproc(target_ulong rb)
return (rb & DBELL_BRDCAST_MASK) == DBELL_BRDCAST_SUBPROC;
}
+/*
+ * Send an interrupt to a thread in the same core as env).
+ */
+static void msgsnd_core_tir(CPUPPCState *env, uint32_t target_tir, int irq)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
+ uint32_t nr_threads = cs->nr_threads;
+
+ if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
+ nr_threads = 1; /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/
+ }
+
+ if (target_tir >= nr_threads) {
+ return;
+ }
+
+ if (nr_threads == 1) {
+ ppc_set_irq(cpu, irq, 1);
+ } else {
+ CPUState *ccs;
+
+ /* Does iothread need to be locked for walking CPU list? */
+ bql_lock();
+ THREAD_SIBLING_FOREACH(cs, ccs) {
+ PowerPCCPU *ccpu = POWERPC_CPU(ccs);
+ if (target_tir == ppc_cpu_tir(ccpu)) {
+ ppc_set_irq(ccpu, irq, 1);
+ break;
+ }
+ }
+ bql_unlock();
+ }
+}
+
void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb)
{
if (!dbell_type_server(rb)) {
@@ -3018,6 +3053,13 @@ void helper_book3s_msgsnd(CPUPPCState *env, target_ulong rb)
return;
}
+ /* POWER8 msgsnd is like msgsndp (targets a thread within core) */
+ if (!(env->insns_flags2 & PPC2_ISA300)) {
+ msgsnd_core_tir(env, rb & PPC_BITMASK(57, 63), PPC_INTERRUPT_HDOORBELL);
+ return;
+ }
+
+ /* POWER9 and later msgsnd is a global (targets any thread) */
cpu = ppc_get_vcpu_by_pir(pir);
if (!cpu) {
return;
@@ -3064,41 +3106,13 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
*/
void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
{
- CPUState *cs = env_cpu(env);
- PowerPCCPU *cpu = env_archcpu(env);
- CPUState *ccs;
- uint32_t nr_threads = cs->nr_threads;
- int ttir = rb & PPC_BITMASK(57, 63);
-
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP);
- if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
- nr_threads = 1; /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/
- }
-
- if (!dbell_type_server(rb) || ttir >= nr_threads) {
- return;
- }
-
- if (nr_threads == 1) {
- ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, 1);
+ if (!dbell_type_server(rb)) {
return;
}
- /* Does iothread need to be locked for walking CPU list? */
- bql_lock();
- THREAD_SIBLING_FOREACH(cs, ccs) {
- PowerPCCPU *ccpu = POWERPC_CPU(ccs);
- uint32_t thread_id = ppc_cpu_tir(ccpu);
-
- if (ttir == thread_id) {
- ppc_set_irq(ccpu, PPC_INTERRUPT_DOORBELL, 1);
- bql_unlock();
- return;
- }
- }
-
- g_assert_not_reached();
+ msgsnd_core_tir(env, rb & PPC_BITMASK(57, 63), PPC_INTERRUPT_DOORBELL);
}
#endif /* TARGET_PPC64 */
--
2.45.1
next prev parent reply other threads:[~2024-07-11 14:19 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-11 14:18 [PATCH 00/18] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-07-11 14:18 ` Nicholas Piggin [this message]
2024-07-11 15:38 ` [PATCH 01/18] target/ppc: Fix msgsnd for POWER8 Cédric Le Goater
2024-07-11 14:18 ` [PATCH 02/18] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-11 14:18 ` [PATCH 03/18] ppc/pnv: Add a pointer from PnvChip to PnvMachineState Nicholas Piggin
2024-07-11 16:09 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 04/18] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-11 14:18 ` [PATCH 05/18] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-11 14:18 ` [PATCH 06/18] ppc/pnv: specialise init for powernv8/9/10 machines Nicholas Piggin
2024-07-11 16:21 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 07/18] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-11 16:22 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 08/18] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-11 16:24 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 09/18] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-11 14:18 ` [PATCH 10/18] ppc: Add has_smt_siblings property to CPUPPCState Nicholas Piggin
2024-07-11 16:34 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 11/18] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-11 16:36 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 12/18] ppc/pnv: Add allow for big-core differences in DT generation Nicholas Piggin
2024-07-11 14:18 ` [PATCH 13/18] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-11 14:18 ` [PATCH 14/18] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-11 14:18 ` [PATCH 15/18] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-11 14:18 ` [PATCH 16/18] ppc/pnv: Add big-core machine property Nicholas Piggin
2024-07-11 14:18 ` [PATCH 17/18] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-11 16:43 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 18/18] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-11 17:00 ` Cédric Le Goater
2024-07-11 17:20 ` [PATCH 00/18] ppc/pnv: Better big-core model, lpar-per-core, PC unit Cédric Le Goater
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