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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cdfa079asm7735735f8f.68.2024.07.11.06.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 06:43:34 -0700 (PDT) Date: Thu, 11 Jul 2024 15:43:33 +0200 From: Igor Mammedov To: Sunil V L Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Michael S . Tsirkin" , Ani Sinha Subject: Re: [PATCH v2 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge Message-ID: <20240711154333.262e0bda@imammedo.users.ipa.redhat.com> In-Reply-To: <20240708114741.3499585-5-sunilvl@ventanamicro.com> References: <20240708114741.3499585-1-sunilvl@ventanamicro.com> <20240708114741.3499585-5-sunilvl@ventanamicro.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.142, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 8 Jul 2024 17:17:36 +0530 Sunil V L wrote: > Currently, PCI link devices (PNP0C0F) are always created within the > scope of the PCI root bridge. However, RISC-V needs these link devices > to be created outside to ensure the probing order in the OS. This > matches the example given in the ACPI specification [1] as well. Hence, > create these link devices directly under _SB instead of under the PCI > root bridge. > > To keep these link device names unique for multiple PCI bridges, change > the device name from GSIx to LXXY format where XX is the PCI bus number > and Y is the INTx. > > GPEX is currently used by riscv, aarch64/virt and x86/microvm machines. > So, this change will alter the DSDT for those systems. > > [1] - ACPI 5.1: 6.2.13.1 Example: Using _PRT to Describe PCI IRQ Routing > > Signed-off-by: Sunil V L > --- > hw/pci-host/gpex-acpi.c | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c > index f69413ea2c..a93b55c991 100644 > --- a/hw/pci-host/gpex-acpi.c > +++ b/hw/pci-host/gpex-acpi.c > @@ -7,7 +7,8 @@ > #include "hw/pci/pcie_host.h" > #include "hw/acpi/cxl.h" > > -static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) > +static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq, > + Aml *scope, uint8_t bus_num) > { > Aml *method, *crs; > int i, slot_no; > @@ -20,7 +21,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) > Aml *pkg = aml_package(4); > aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); > aml_append(pkg, aml_int(i)); > - aml_append(pkg, aml_name("GSI%d", gsi)); > + aml_append(pkg, aml_name("L%.02X%d", bus_num, gsi)); instead of mixing hex and decimal here, make gsi hex as well to be consistent? > aml_append(pkg, aml_int(0)); > aml_append(rt_pkg, pkg); > } > @@ -30,7 +31,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) > /* Create GSI link device */ > for (i = 0; i < PCI_NUM_PINS; i++) { > uint32_t irqs = irq + i; > - Aml *dev_gsi = aml_device("GSI%d", i); > + Aml *dev_gsi = aml_device("L%.02X%d", bus_num, i); ditto > aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); > aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); > crs = aml_resource_template(); > @@ -45,7 +46,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) > aml_append(dev_gsi, aml_name_decl("_CRS", crs)); > method = aml_method("_SRS", 1, AML_NOTSERIALIZED); > aml_append(dev_gsi, method); > - aml_append(dev, dev_gsi); > + aml_append(scope, dev_gsi); > } > } > > @@ -174,7 +175,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); > } > > - acpi_dsdt_add_pci_route_table(dev, cfg->irq); > + acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, bus_num); > > /* > * Resources defined for PXBs are composed of the following parts: > @@ -205,7 +206,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); > aml_append(dev, aml_name_decl("_CCA", aml_int(1))); > > - acpi_dsdt_add_pci_route_table(dev, cfg->irq); > + acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, 0); > > method = aml_method("_CBA", 0, AML_NOTSERIALIZED); > aml_append(method, aml_return(aml_int(cfg->ecam.base)));