From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-devel@nongnu.org
Subject: [PATCH v2 11/19] ppc/pnv: Add allow for big-core differences in DT generation
Date: Fri, 12 Jul 2024 22:02:38 +1000 [thread overview]
Message-ID: <20240712120247.477133-12-npiggin@gmail.com> (raw)
In-Reply-To: <20240712120247.477133-1-npiggin@gmail.com>
device-tree building needs to account for big-core mode, because it is
driven by qemu cores (small cores). Every second core should be skipped,
and every core should describe threads for both small-cores that make
up the big core.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 43 +++++++++++++++++++++++++++++++++++--------
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 555a983536..fdf66323b8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -141,9 +141,9 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip);
- g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
+ uint32_t *servers_prop;
int i;
- uint32_t pir;
+ uint32_t pir, tir;
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
0xffffffff, 0xffffffff};
uint32_t tbfreq = PNV_TIMEBASE_FREQ;
@@ -154,7 +154,10 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
char *nodename;
int cpus_offset = get_cpus_node(fdt);
- pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, NULL);
+ pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir);
+
+ /* Only one DT node per (big) core */
+ g_assert(tir == 0);
nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
offset = fdt_add_subnode(fdt, cpus_offset, nodename);
@@ -235,12 +238,28 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
}
/* Build interrupt servers properties */
- for (i = 0; i < smt_threads; i++) {
- pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
- servers_prop[i] = cpu_to_be32(pir);
+ if (pc->big_core) {
+ servers_prop = g_new(uint32_t, smt_threads * 2);
+ for (i = 0; i < smt_threads; i++) {
+ pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
+ servers_prop[i * 2] = cpu_to_be32(pir);
+
+ pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL);
+ servers_prop[i * 2 + 1] = cpu_to_be32(pir);
+ }
+ _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
+ servers_prop, sizeof(*servers_prop) * smt_threads
+ * 2)));
+ } else {
+ servers_prop = g_new(uint32_t, smt_threads);
+ for (i = 0; i < smt_threads; i++) {
+ pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
+ servers_prop[i] = cpu_to_be32(pir);
+ }
+ _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
+ servers_prop, sizeof(*servers_prop) * smt_threads)));
}
- _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
- servers_prop, sizeof(*servers_prop) * smt_threads)));
+ g_free(servers_prop);
return offset;
}
@@ -389,6 +408,10 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
pa_features_300, sizeof(pa_features_300))));
+
+ if (pnv_core->big_core) {
+ i++; /* Big-core groups two QEMU cores */
+ }
}
if (chip->ram_size) {
@@ -450,6 +473,10 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
pa_features_31, sizeof(pa_features_31))));
+
+ if (pnv_core->big_core) {
+ i++; /* Big-core groups two QEMU cores */
+ }
}
if (chip->ram_size) {
--
2.45.1
next prev parent reply other threads:[~2024-07-12 12:23 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-12 12:02 [PATCH v2 00/19] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 01/19] target/ppc: Fix msgsnd for POWER8 Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 02/19] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 03/19] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-12 13:40 ` Cédric Le Goater
2024-07-15 6:30 ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 04/19] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 05/19] ppc/pnv: use class attribute to limit SMT threads for different machines Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 06/19] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 07/19] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 08/19] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 09/19] ppc: Add has_smt_siblings property to CPUPPCState Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 10/19] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-13 7:19 ` Cédric Le Goater
2024-07-15 6:31 ` Nicholas Piggin
2024-07-12 12:02 ` Nicholas Piggin [this message]
2024-07-12 12:02 ` [PATCH v2 12/19] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-13 7:28 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-13 7:22 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 15/19] ppc/pnv: Add big-core machine property Nicholas Piggin
2024-07-13 7:24 ` Cédric Le Goater
2024-07-15 6:32 ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 16/19] system/cpus: Add cpu_pause() function Nicholas Piggin
2024-07-12 14:35 ` Philippe Mathieu-Daudé
2024-07-12 15:25 ` Peter Xu
2024-07-12 12:02 ` [PATCH v2 17/19] ppc/pnv: Add a CPU nmi and resume function Nicholas Piggin
2024-07-13 7:27 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 18/19] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 19/19] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-13 7:27 ` Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240712120247.477133-12-npiggin@gmail.com \
--to=npiggin@gmail.com \
--cc=clg@kaod.org \
--cc=fbarrat@linux.ibm.com \
--cc=harshpb@linux.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).