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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Frédéric Barrat" <fbarrat@linux.ibm.com>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
	qemu-devel@nongnu.org
Subject: [PATCH v2 15/19] ppc/pnv: Add big-core machine property
Date: Fri, 12 Jul 2024 22:02:42 +1000	[thread overview]
Message-ID: <20240712120247.477133-16-npiggin@gmail.com> (raw)
In-Reply-To: <20240712120247.477133-1-npiggin@gmail.com>

Big-core implementation is complete, so expose it as a machine
property that may be set with big-core=on option on powernv9 and
powernv10 machines.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/ppc/pnv.c      | 62 +++++++++++++++++++++++++++++++++++------------
 hw/ppc/pnv_core.c |  2 +-
 2 files changed, 47 insertions(+), 17 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 24f7c007ce..e405d416ff 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2338,6 +2338,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
                                  &error_abort);
 
         pnv_core->tod_state.big_core_quirk = pmc->quirk_tb_big_core;
+        pnv_core->big_core = chip->big_core;
 
         qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
 
@@ -2578,6 +2579,34 @@ static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
     return total_count;
 }
 
+static bool pnv_machine_get_big_core(Object *obj, Error **errp)
+{
+    PnvMachineState *pnv = PNV_MACHINE(obj);
+    return pnv->big_core;
+}
+
+static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp)
+{
+    PnvMachineState *pnv = PNV_MACHINE(obj);
+    pnv->big_core = value;
+}
+
+static bool pnv_machine_get_hb(Object *obj, Error **errp)
+{
+    PnvMachineState *pnv = PNV_MACHINE(obj);
+
+    return !!pnv->fw_load_addr;
+}
+
+static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
+{
+    PnvMachineState *pnv = PNV_MACHINE(obj);
+
+    if (value) {
+        pnv->fw_load_addr = 0x8000000;
+    }
+}
+
 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -2629,6 +2658,12 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
     pmc->dt_power_mgt = pnv_dt_power_mgt;
 
     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
+
+    object_class_property_add_bool(oc, "big-core",
+                                   pnv_machine_get_big_core,
+                                   pnv_machine_set_big_core);
+    object_class_property_set_description(oc, "big-core",
+                              "Use big-core (aka fused-core) mode");
 }
 
 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
@@ -2665,6 +2700,17 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
 
     pnv_machine_p10_common_class_init(oc, data);
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
+
+    /*
+     * This is the parent of POWER10 Rainier class, so properies go here
+     * rather than common init (which would add them to both parent and
+     * child which is invalid).
+     */
+    object_class_property_add_bool(oc, "big-core",
+                                   pnv_machine_get_big_core,
+                                   pnv_machine_set_big_core);
+    object_class_property_set_description(oc, "big-core",
+                              "Use big-core (aka fused-core) mode");
 }
 
 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
@@ -2677,22 +2723,6 @@ static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
     pmc->i2c_init = pnv_rainier_i2c_init;
 }
 
-static bool pnv_machine_get_hb(Object *obj, Error **errp)
-{
-    PnvMachineState *pnv = PNV_MACHINE(obj);
-
-    return !!pnv->fw_load_addr;
-}
-
-static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
-{
-    PnvMachineState *pnv = PNV_MACHINE(obj);
-
-    if (value) {
-        pnv->fw_load_addr = 0x8000000;
-    }
-}
-
 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
 {
     CPUPPCState *env = cpu_env(cs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index a96ec4e2b9..238a4cd4ab 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -296,7 +296,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
         obj = object_new(typename);
         cpu = POWERPC_CPU(obj);
 
-        pc->threads[i] = POWERPC_CPU(obj);
+        pc->threads[i] = cpu;
         if (cc->nr_threads > 1) {
             cpu->env.has_smt_siblings = true;
         }
-- 
2.45.1



  parent reply	other threads:[~2024-07-12 12:29 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-12 12:02 [PATCH v2 00/19] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 01/19] target/ppc: Fix msgsnd for POWER8 Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 02/19] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 03/19] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-12 13:40   ` Cédric Le Goater
2024-07-15  6:30     ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 04/19] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 05/19] ppc/pnv: use class attribute to limit SMT threads for different machines Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 06/19] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 07/19] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 08/19] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 09/19] ppc: Add has_smt_siblings property to CPUPPCState Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 10/19] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-13  7:19   ` Cédric Le Goater
2024-07-15  6:31     ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 11/19] ppc/pnv: Add allow for big-core differences in DT generation Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 12/19] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-13  7:28   ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-13  7:22   ` Cédric Le Goater
2024-07-12 12:02 ` Nicholas Piggin [this message]
2024-07-13  7:24   ` [PATCH v2 15/19] ppc/pnv: Add big-core machine property Cédric Le Goater
2024-07-15  6:32     ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 16/19] system/cpus: Add cpu_pause() function Nicholas Piggin
2024-07-12 14:35   ` Philippe Mathieu-Daudé
2024-07-12 15:25   ` Peter Xu
2024-07-12 12:02 ` [PATCH v2 17/19] ppc/pnv: Add a CPU nmi and resume function Nicholas Piggin
2024-07-13  7:27   ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 18/19] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 19/19] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-13  7:27   ` Cédric Le Goater

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