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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3680dafb939sm6451539f8f.89.2024.07.15.06.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jul 2024 06:39:24 -0700 (PDT) Date: Mon, 15 Jul 2024 15:39:23 +0200 From: Igor Mammedov To: Salil Mehta Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Shaoqin Huang , Zhao Liu Subject: Re: [PATCH V15 5/7] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Message-ID: <20240715153923.60f9a2f1@imammedo.users.ipa.redhat.com> In-Reply-To: <20240713182516.1457-6-salil.mehta@huawei.com> References: <20240713182516.1457-1-salil.mehta@huawei.com> <20240713182516.1457-6-salil.mehta@huawei.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, 13 Jul 2024 19:25:14 +0100 Salil Mehta wrote: > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO port > based and existing CPUs AML code assumes _CRS objects would evaluate to a system > resource which describes IO Port address. But on ARM arch CPUs control > device(\\_SB.PRES) register interface is memory-mapped hence _CRS object should > evaluate to system resource which describes memory-mapped base address. Update > build CPUs AML function to accept both IO/MEMORY region spaces and accordingly > update the _CRS object. > > Co-developed-by: Keqian Zhu > Signed-off-by: Keqian Zhu > Signed-off-by: Salil Mehta > Reviewed-by: Gavin Shan > Tested-by: Vishnu Pajjuri > Reviewed-by: Jonathan Cameron > Tested-by: Xianglai Li > Tested-by: Miguel Luis > Reviewed-by: Shaoqin Huang > Tested-by: Zhao Liu Reviewed-by: Igor Mammedov > --- > hw/acpi/cpu.c | 17 +++++++++++++---- > hw/i386/acpi-build.c | 3 ++- > include/hw/acpi/cpu.h | 5 +++-- > 3 files changed, 18 insertions(+), 7 deletions(-) > > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c > index cf5e9183e4..5cb60ca8bc 100644 > --- a/hw/acpi/cpu.c > +++ b/hw/acpi/cpu.c > @@ -338,9 +338,10 @@ const VMStateDescription vmstate_cpu_hotplug = { > #define CPU_FW_EJECT_EVENT "CEJF" > > void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, > - build_madt_cpu_fn build_madt_cpu, hwaddr io_base, > + build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, > const char *res_root, > - const char *event_handler_method) > + const char *event_handler_method, > + AmlRegionSpace rs) > { > Aml *ifctx; > Aml *field; > @@ -364,14 +365,22 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, > aml_name_decl("_UID", aml_string("CPU Hotplug resources"))); > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); > > + assert((rs == AML_SYSTEM_IO) || (rs == AML_SYSTEM_MEMORY)); > + > crs = aml_resource_template(); > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, > + if (rs == AML_SYSTEM_IO) { > + aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, 1, > ACPI_CPU_HOTPLUG_REG_LEN)); > + } else if (rs == AML_SYSTEM_MEMORY) { > + aml_append(crs, aml_memory32_fixed(base_addr, > + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE)); > + } > + > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); > > /* declare CPU hotplug MMIO region with related access fields */ > aml_append(cpu_ctrl_dev, > - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base), > + aml_operation_region("PRST", rs, aml_int(base_addr), > ACPI_CPU_HOTPLUG_REG_LEN)); > > field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index f4e366f64f..5d4bd2b710 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -1536,7 +1536,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > .fw_unplugs_cpu = pm->smi_on_cpu_unplug, > }; > build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, > - pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02"); > + pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", > + AML_SYSTEM_IO); > } > > if (pcms->memhp_io_base && nr_mem) { > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h > index df87b15997..32654dc274 100644 > --- a/include/hw/acpi/cpu.h > +++ b/include/hw/acpi/cpu.h > @@ -63,9 +63,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const CPUArchIdList *apic_ids, > GArray *entry, bool force_enabled); > > void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, > - build_madt_cpu_fn build_madt_cpu, hwaddr io_base, > + build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, > const char *res_root, > - const char *event_handler_method); > + const char *event_handler_method, > + AmlRegionSpace rs); > > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list); >